svn commit: r290769 - in head/sys: arm/conf boot/fdt/dts/arm
Warner Losh
imp at FreeBSD.org
Fri Nov 13 15:36:42 UTC 2015
Author: imp
Date: Fri Nov 13 15:36:40 2015
New Revision: 290769
URL: https://svnweb.freebsd.org/changeset/base/290769
Log:
Add support for the Zybo and similar boards to ZEDBOARD kernel.
Zybo needs its own DTB and has a different PHY, so add it to
the base kernel. Details on building bootable SD images at
http://www.thomasskibo.com/zedbsd/
Submitted By: Thomas Skibo
Added:
head/sys/boot/fdt/dts/arm/zybo.dts (contents, props changed)
Modified:
head/sys/arm/conf/ZEDBOARD
Modified: head/sys/arm/conf/ZEDBOARD
==============================================================================
--- head/sys/arm/conf/ZEDBOARD Fri Nov 13 10:34:14 2015 (r290768)
+++ head/sys/arm/conf/ZEDBOARD Fri Nov 13 15:36:40 2015 (r290769)
@@ -1,6 +1,6 @@
#
# ZEDBOARD -- Custom configuration for the Xilinx Zynq-7000 based
-# ZedBoard (www.zedboard.org)
+# ZedBoard (www.zedboard.org) and similar Zynq boards.
#
# For more information on this file, please read the config(5) manual page,
# and/or the handbook section on Kernel Configuration Files:
@@ -59,6 +59,7 @@ device ether
device cgem # Zynq-7000 gig ethernet device
device mii
device e1000phy
+device rgephy # Zybo uses Realtek RTL8211E
device pty
device uart
device gpio
Added: head/sys/boot/fdt/dts/arm/zybo.dts
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/zybo.dts Fri Nov 13 15:36:40 2015 (r290769)
@@ -0,0 +1,216 @@
+/*-
+ * Copyright (c) 2015 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "zybo";
+ compatible = "digilent,zybo";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&GIC>;
+
+ // cpus {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // cpu at 0 {
+ // device-type = "cpu";
+ // model = "ARM Cortex-A9";
+ // };
+ // };
+
+ memory {
+ // First megabyte isn't accessible by all interconnect masters.
+ device_type = "memory";
+ reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
+ };
+
+ // Zynq PS System registers.
+ //
+ ps7sys at f8000000 {
+ device_type = "soc";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8000000 0xf10000>;
+
+ // SLCR block
+ slcr: slcr at 7000 {
+ compatible = "xlnx,zy7_slcr";
+ reg = <0x0 0x1000>;
+ clock-frequency = <50000000>; // 50Mhz PS_CLK
+ };
+
+ // Interrupt controller
+ GIC: gic {
+ compatible = "arm,gic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0xf01000 0x1000>, // distributer registers
+ <0xf00100 0x0100>; // CPU if registers
+ };
+
+ // L2 cache controller
+ pl310 at f02000 {
+ compatible = "arm,pl310";
+ reg = <0xf02000 0x1000>;
+ interrupts = <34>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // Device Config
+ devcfg: devcfg at 7000 {
+ compatible = "xlnx,zy7_devcfg";
+ reg = <0x7000 0x1000>;
+ interrupts = <40>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // triple timer counters0,1
+ ttc0: ttc at 1000 {
+ compatible = "xlnx,ttc";
+ reg = <0x1000 0x1000>;
+ };
+ ttc1: ttc at 2000 {
+ compatible = "xlnx,ttc";
+ reg = <0x2000 0x1000>;
+ };
+
+ // ARM Cortex A9 TWD Timer
+ timer at f00600 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = <325000000>; // 325Mhz
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf00200 0x100>, // Global Timer Regs
+ <0xf00600 0x20>; // Private Timer Regs
+ interrupts = < 27 29 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ // system watch-dog timer
+ swdt at 5000 {
+ device_type = "watchdog";
+ compatible = "xlnx,zy7_wdt";
+ reg = <0x5000 0x1000>;
+ interrupts = <41>;
+ interrupt-parent = <&GIC>;
+ };
+
+ scuwdt at f00620 {
+ device_type = "watchdog";
+ compatible = "arm,mpcore_wdt";
+ reg = <0xf00620 0x20>;
+ interrupts = <30>;
+ interrupt-parent = <&GIC>;
+ reset = <1>;
+ };
+ }; // pssys at f8000000
+
+ // Zynq PS I/O Peripheral registers.
+ //
+ ps7io at e0000000 {
+ device_type = "soc";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0000000 0x300000>;
+
+ // uart0: uart at 0000 {
+ // device_type = "serial";
+ // compatible = "cadence,uart";
+ // reg = <0x0000 0x1000>;
+ // interrupts = <59>;
+ // interrupt-parent = <&GIC>;
+ // clock-frequency = <50000000>;
+ // };
+
+ uart1: uart at 1000 {
+ device_type = "serial";
+ compatible = "cadence,uart";
+ reg = <0x1000 0x1000>;
+ interrupts = <82>;
+ interrupt-parent = <&GIC>;
+ clock-frequency = <50000000>;
+ current-speed = <115200>;
+ };
+
+ gpio: gpio at a000 {
+ compatible = "xlnx,zy7_gpio";
+ reg = <0xa000 0x1000>;
+ interrupts = <52>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // GigE
+ eth0: eth at b000 {
+ // device_type = "network";
+
+ compatible = "cadence,gem";
+ reg = <0xb000 0x1000>;
+ interrupts = <54 55>;
+ interrupt-parent = <&GIC>;
+ ref-clock-num = <0>;
+ };
+
+ // SDIO
+ sdhci0: sdhci at 100000 {
+ compatible = "xlnx,zy7_sdhci";
+ reg = <0x100000 0x1000>;
+ interrupts = <56>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <50000000>;
+ };
+
+ // QSPI
+ qspi0: qspi at d000 {
+ compatible = "xlnx,zy7_qspi";
+ reg = <0xd000 0x1000>;
+ interrupts = <51>;
+ interrupt-parent = <&GIC>;
+ spi-clock = <50000000>;
+ ref-clock = <200000000>;
+ };
+
+ // USB
+ ehci0: ehci at 2000 {
+ compatible = "xlnx,zy7_ehci";
+ reg = <0x2000 0x1000>;
+ interrupts = <53>;
+ interrupt-parent = <&GIC>;
+ };
+
+ }; // ps7io at e0000000
+
+ chosen {
+ stdin = &uart1;
+ stdout = &uart1;
+ };
+};
+
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