svn commit: r291689 - in head/sys: conf dev/ahci
Andrew Turner
andrew at FreeBSD.org
Thu Dec 3 11:24:13 UTC 2015
Author: andrew
Date: Thu Dec 3 11:24:11 2015
New Revision: 291689
URL: https://svnweb.freebsd.org/changeset/base/291689
Log:
Add support for a generic AHCI attachment. This allows us to attach to a
typically memory mapped bus, for example on the AMD Opteron A1100 the AHCI
device is mapped in the CPUs address space, and not through a PCI
controller.
Further work is needed for this to work with ACPI as this is expected to be
common on ARMv8 servers.
Reviewed by: mav, mmel
Obtained from: mmel, ABT Systems Ltd
Relnotes: yes
Sponsored by: SoftIron Inc
Differential Revision: https://reviews.freebsd.org/D4269
Added:
head/sys/dev/ahci/ahci_generic.c
- copied, changed from r291244, head/sys/dev/ahci/ahci_pci.c
Modified:
head/sys/conf/files.arm64
Modified: head/sys/conf/files.arm64
==============================================================================
--- head/sys/conf/files.arm64 Thu Dec 3 11:14:14 2015 (r291688)
+++ head/sys/conf/files.arm64 Thu Dec 3 11:24:11 2015 (r291689)
@@ -57,6 +57,7 @@ arm64/cloudabi64/cloudabi64_sysvec.c opt
crypto/blowfish/bf_enc.c optional crypto | ipsec
crypto/des/des_enc.c optional crypto | ipsec | netsmb
dev/acpica/acpi_if.m optional acpi
+dev/ahci/ahci_generic.c optional ahci fdt
dev/fdt/fdt_arm64.c optional fdt
dev/hwpmc/hwpmc_arm64.c optional hwpmc
dev/hwpmc/hwpmc_arm64_md.c optional hwpmc
Copied and modified: head/sys/dev/ahci/ahci_generic.c (from r291244, head/sys/dev/ahci/ahci_pci.c)
==============================================================================
--- head/sys/dev/ahci/ahci_pci.c Tue Nov 24 09:45:36 2015 (r291244, copy source)
+++ head/sys/dev/ahci/ahci_generic.c Thu Dec 3 11:24:11 2015 (r291689)
@@ -37,559 +37,83 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
-#include <machine/stdarg.h>
-#include <machine/resource.h>
-#include <machine/bus.h>
#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include "ahci.h"
-
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
-
-static const struct {
- uint32_t id;
- uint8_t rev;
- const char *name;
- int quirks;
-} ahci_ids[] = {
- {0x43801002, 0x00, "AMD SB600",
- AHCI_Q_NOMSI | AHCI_Q_ATI_PMP_BUG | AHCI_Q_MAXIO_64K},
- {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
- AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
- {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
- AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
- {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
- AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
- {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
- AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
- {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
- AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
- /* Not sure SB8x0/SB9x0 needs this quirk. Be conservative though */
- {0x43951002, 0x00, "AMD SB8x0/SB9x0", AHCI_Q_ATI_PMP_BUG},
- {0x78001022, 0x00, "AMD Hudson-2", 0},
- {0x78011022, 0x00, "AMD Hudson-2", 0},
- {0x78021022, 0x00, "AMD Hudson-2", 0},
- {0x78031022, 0x00, "AMD Hudson-2", 0},
- {0x78041022, 0x00, "AMD Hudson-2", 0},
- {0x06111b21, 0x00, "ASMedia ASM2106", 0},
- {0x06121b21, 0x00, "ASMedia ASM1061", 0},
- {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
- {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
- {0x26818086, 0x00, "Intel ESB2", 0},
- {0x26828086, 0x00, "Intel ESB2", 0},
- {0x26838086, 0x00, "Intel ESB2", 0},
- {0x27c18086, 0x00, "Intel ICH7", 0},
- {0x27c38086, 0x00, "Intel ICH7", 0},
- {0x27c58086, 0x00, "Intel ICH7M", 0},
- {0x27c68086, 0x00, "Intel ICH7M", 0},
- {0x28218086, 0x00, "Intel ICH8", 0},
- {0x28228086, 0x00, "Intel ICH8", 0},
- {0x28248086, 0x00, "Intel ICH8", 0},
- {0x28298086, 0x00, "Intel ICH8M", 0},
- {0x282a8086, 0x00, "Intel ICH8M", 0},
- {0x29228086, 0x00, "Intel ICH9", 0},
- {0x29238086, 0x00, "Intel ICH9", 0},
- {0x29248086, 0x00, "Intel ICH9", 0},
- {0x29258086, 0x00, "Intel ICH9", 0},
- {0x29278086, 0x00, "Intel ICH9", 0},
- {0x29298086, 0x00, "Intel ICH9M", 0},
- {0x292a8086, 0x00, "Intel ICH9M", 0},
- {0x292b8086, 0x00, "Intel ICH9M", 0},
- {0x292c8086, 0x00, "Intel ICH9M", 0},
- {0x292f8086, 0x00, "Intel ICH9M", 0},
- {0x294d8086, 0x00, "Intel ICH9", 0},
- {0x294e8086, 0x00, "Intel ICH9M", 0},
- {0x3a058086, 0x00, "Intel ICH10", 0},
- {0x3a228086, 0x00, "Intel ICH10", 0},
- {0x3a258086, 0x00, "Intel ICH10", 0},
- {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x1c028086, 0x00, "Intel Cougar Point", 0},
- {0x1c038086, 0x00, "Intel Cougar Point", 0},
- {0x1c048086, 0x00, "Intel Cougar Point", 0},
- {0x1c058086, 0x00, "Intel Cougar Point", 0},
- {0x1d028086, 0x00, "Intel Patsburg", 0},
- {0x1d048086, 0x00, "Intel Patsburg", 0},
- {0x1d068086, 0x00, "Intel Patsburg", 0},
- {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
- {0x1e028086, 0x00, "Intel Panther Point", 0},
- {0x1e038086, 0x00, "Intel Panther Point", 0},
- {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1f228086, 0x00, "Intel Avoton", 0},
- {0x1f238086, 0x00, "Intel Avoton", 0},
- {0x1f248086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f258086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f268086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f278086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f328086, 0x00, "Intel Avoton", 0},
- {0x1f338086, 0x00, "Intel Avoton", 0},
- {0x1f348086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f358086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f368086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f378086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x23a38086, 0x00, "Intel Coleto Creek", 0},
- {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8c028086, 0x00, "Intel Lynx Point", 0},
- {0x8c038086, 0x00, "Intel Lynx Point", 0},
- {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c828086, 0x00, "Intel Wildcat Point", 0},
- {0x8c838086, 0x00, "Intel Wildcat Point", 0},
- {0x8c848086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c858086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c868086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c878086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c8e8086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c8f8086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8d028086, 0x00, "Intel Wellsburg", 0},
- {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d628086, 0x00, "Intel Wellsburg", 0},
- {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x9c028086, 0x00, "Intel Lynx Point-LP", 0},
- {0x9c038086, 0x00, "Intel Lynx Point-LP", 0},
- {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x23238086, 0x00, "Intel DH89xxCC", 0},
- {0x2360197b, 0x00, "JMicron JMB360", 0},
- {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
- {0x2362197b, 0x00, "JMicron JMB362", 0},
- {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
- {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
- {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
- {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
- {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
- AHCI_Q_1CH | AHCI_Q_EDGEIS},
- {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
- AHCI_Q_2CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
- AHCI_Q_4CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
- AHCI_Q_4CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS},
- {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG},
- {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2},
- {0x91251b4b, 0x00, "Marvell 88SE9125", 0},
- {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG},
- {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG},
- {0x91721b4b, 0x00, "Marvell 88SE9172", 0},
- {0x91821b4b, 0x00, "Marvell 88SE9182", 0},
- {0x91831b4b, 0x00, "Marvell 88SS9183", 0},
- {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0},
- {0x92151b4b, 0x00, "Marvell 88SE9215", 0},
- {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG},
- {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG},
- {0x92351b4b, 0x00, "Marvell 88SE9235", 0},
- {0x06201103, 0x00, "HighPoint RocketRAID 620", 0},
- {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0},
- {0x06221103, 0x00, "HighPoint RocketRAID 622", 0},
- {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0},
- {0x06401103, 0x00, "HighPoint RocketRAID 640", 0},
- {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0},
- {0x06441103, 0x00, "HighPoint RocketRAID 644", 0},
- {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0},
- {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0},
- {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0},
- {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0},
- {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
- {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x3781105a, 0x00, "Promise TX8660", 0},
- {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
- {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
- {0x11841039, 0x00, "SiS 966", 0},
- {0x11851039, 0x00, "SiS 968", 0},
- {0x01861039, 0x00, "SiS 968", 0},
- {0xa01c177d, 0x00, "ThunderX", AHCI_Q_ABAR0|AHCI_Q_1MSI},
- {0x00311c36, 0x00, "Annapurna", AHCI_Q_FORCE_PI|AHCI_Q_RESTORE_CAP},
- {0x00000000, 0x00, NULL, 0}
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/ahci/ahci.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+static struct ofw_compat_data compat_data[] = {
+ {"generic-ahci", 1},
+ {"snps,dwc-ahci", 1},
+ {NULL, 0}
};
static int
-ahci_pci_ctlr_reset(device_t dev)
+ahci_gen_ctlr_reset(device_t dev)
{
- if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
- (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
- pci_write_config(dev, 0x92, 0x01, 1);
return ahci_ctlr_reset(dev);
}
static int
ahci_probe(device_t dev)
{
- char buf[64];
- int i, valid = 0;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
-
- /*
- * Ensure it is not a PCI bridge (some vendors use
- * the same PID and VID in PCI bridge and AHCI cards).
- */
- if (pci_get_class(dev) == PCIC_BRIDGE)
- return (ENXIO);
- /* Is this a possible AHCI candidate? */
- if (pci_get_class(dev) == PCIC_STORAGE &&
- pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
- pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
- valid = 1;
- else if (pci_get_class(dev) == PCIC_STORAGE &&
- pci_get_subclass(dev) == PCIS_STORAGE_RAID)
- valid = 2;
- /* Is this a known AHCI chip? */
- for (i = 0; ahci_ids[i].id != 0; i++) {
- if (ahci_ids[i].id == devid &&
- ahci_ids[i].rev <= revid &&
- (valid || (force_ahci == 1 &&
- !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
- /* Do not attach JMicrons with single PCI function. */
- if (pci_get_vendor(dev) == 0x197b &&
- (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
- return (ENXIO);
- snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
- ahci_ids[i].name);
- device_set_desc_copy(dev, buf);
- return (BUS_PROBE_DEFAULT);
- }
- }
- if (valid != 1)
+ if (!ofw_bus_status_okay(dev))
return (ENXIO);
- device_set_desc_copy(dev, "AHCI SATA controller");
- return (BUS_PROBE_DEFAULT);
-}
-
-static int
-ahci_ata_probe(device_t dev)
-{
- char buf[64];
- int i;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
- if ((intptr_t)device_get_ivars(dev) >= 0)
+ if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
return (ENXIO);
- /* Is this a known AHCI chip? */
- for (i = 0; ahci_ids[i].id != 0; i++) {
- if (ahci_ids[i].id == devid &&
- ahci_ids[i].rev <= revid) {
- snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
- ahci_ids[i].name);
- device_set_desc_copy(dev, buf);
- return (BUS_PROBE_DEFAULT);
- }
- }
+
device_set_desc_copy(dev, "AHCI SATA controller");
return (BUS_PROBE_DEFAULT);
}
static int
-ahci_pci_read_msix_bars(device_t dev, uint8_t *table_bar, uint8_t *pba_bar)
-{
- int cap_offset = 0, ret;
- uint32_t val;
-
- if ((table_bar == NULL) || (pba_bar == NULL))
- return (EINVAL);
-
- ret = pci_find_cap(dev, PCIY_MSIX, &cap_offset);
- if (ret != 0)
- return (EINVAL);
-
- val = pci_read_config(dev, cap_offset + PCIR_MSIX_TABLE, 4);
- *table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
-
- val = pci_read_config(dev, cap_offset + PCIR_MSIX_PBA, 4);
- *pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
-
- return (0);
-}
-
-static int
-ahci_pci_attach(device_t dev)
+ahci_gen_attach(device_t dev)
{
struct ahci_controller *ctlr = device_get_softc(dev);
- int error, i;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
- int msi_count, msix_count;
- uint8_t table_bar = 0, pba_bar = 0;
-
- msi_count = pci_msi_count(dev);
- msix_count = pci_msix_count(dev);
-
- i = 0;
- while (ahci_ids[i].id != 0 &&
- (ahci_ids[i].id != devid ||
- ahci_ids[i].rev > revid))
- i++;
- ctlr->quirks = ahci_ids[i].quirks;
- /* Limit speed for my onboard JMicron external port.
- * It is not eSATA really, limit to SATA 1 */
- if (pci_get_devid(dev) == 0x2363197b &&
- pci_get_subvendor(dev) == 0x1043 &&
- pci_get_subdevice(dev) == 0x81e4)
- ctlr->quirks |= AHCI_Q_SATA1_UNIT0;
- ctlr->vendorid = pci_get_vendor(dev);
- ctlr->deviceid = pci_get_device(dev);
- ctlr->subvendorid = pci_get_subvendor(dev);
- ctlr->subdeviceid = pci_get_subdevice(dev);
-
- /* Default AHCI Base Address is BAR(5), Cavium uses BAR(0) */
- if (ctlr->quirks & AHCI_Q_ABAR0)
- ctlr->r_rid = PCIR_BAR(0);
- else
- ctlr->r_rid = PCIR_BAR(5);
- if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &ctlr->r_rid, RF_ACTIVE)))
- return ENXIO;
-
- /* Read MSI-x BAR IDs if supported */
- if (msix_count > 0) {
- error = ahci_pci_read_msix_bars(dev, &table_bar, &pba_bar);
- if (error == 0) {
- ctlr->r_msix_tab_rid = table_bar;
- ctlr->r_msix_pba_rid = pba_bar;
- } else {
- /* Failed to read BARs, disable MSI-x */
- msix_count = 0;
- }
- }
+ int error;
- /* Allocate resources for MSI-x table and PBA */
- if (msix_count > 0) {
- /*
- * Allocate new MSI-x table only if not
- * allocated before.
- */
- ctlr->r_msix_table = NULL;
- if (ctlr->r_msix_tab_rid != ctlr->r_rid) {
- /* Separate BAR for MSI-x */
- ctlr->r_msix_table = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &ctlr->r_msix_tab_rid, RF_ACTIVE);
- if (ctlr->r_msix_table == NULL) {
- ahci_free_mem(dev);
- return (ENXIO);
- }
- }
-
- /*
- * Allocate new PBA table only if not
- * allocated before.
- */
- ctlr->r_msix_pba = NULL;
- if ((ctlr->r_msix_pba_rid != ctlr->r_msix_tab_rid) &&
- (ctlr->r_msix_pba_rid != ctlr->r_rid)) {
- /* Separate BAR for PBA */
- ctlr->r_msix_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &ctlr->r_msix_pba_rid, RF_ACTIVE);
- if (ctlr->r_msix_pba == NULL) {
- ahci_free_mem(dev);
- return (ENXIO);
- }
- }
- }
+ ctlr->r_rid = 0;
+ ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ctlr->r_rid,
+ RF_ACTIVE);
+ if (ctlr->r_mem == NULL)
+ return (ENXIO);
- pci_enable_busmaster(dev);
- /* Reset controller */
- if ((error = ahci_pci_ctlr_reset(dev)) != 0) {
- ahci_free_mem(dev);
- return (error);
- };
-
- /* Setup interrupts. */
-
- /* Setup MSI register parameters */
- /* Process hints. */
- if (ctlr->quirks & AHCI_Q_NOMSI)
- ctlr->msi = 0;
- else if (ctlr->quirks & AHCI_Q_1MSI)
- ctlr->msi = 1;
- else
- ctlr->msi = 2;
- resource_int_value(device_get_name(dev),
- device_get_unit(dev), "msi", &ctlr->msi);
+ /* Setup controller defaults. */
ctlr->numirqs = 1;
- if (msi_count == 0 && msix_count == 0)
- ctlr->msi = 0;
- if (ctlr->msi < 0)
- ctlr->msi = 0;
- else if (ctlr->msi == 1) {
- msi_count = min(1, msi_count);
- msix_count = min(1, msix_count);
- } else if (ctlr->msi > 1)
- ctlr->msi = 2;
-
- /* Allocate MSI/MSI-x if needed/present. */
- if (ctlr->msi > 0) {
- error = ENXIO;
-
- /* Try to allocate MSI-x first */
- if (msix_count > 0) {
- error = pci_alloc_msix(dev, &msix_count);
- if (error == 0)
- ctlr->numirqs = msix_count;
- }
-
- /*
- * Try to allocate MSI if msi_count is greater than 0
- * and if MSI-x allocation failed.
- */
- if ((error != 0) && (msi_count > 0)) {
- error = pci_alloc_msi(dev, &msi_count);
- if (error == 0)
- ctlr->numirqs = msi_count;
- }
-
- /* Both MSI and MSI-x allocations failed */
- if (error != 0) {
- ctlr->msi = 0;
- device_printf(dev, "Failed to allocate MSI/MSI-x, "
- "falling back to INTx\n");
- }
- }
- error = ahci_attach(dev);
+ /* Reset controller */
+ if ((error = ahci_gen_ctlr_reset(dev)) == 0)
+ error = ahci_attach(dev);
+
if (error != 0) {
- if (ctlr->msi > 0)
- pci_release_msi(dev);
- ahci_free_mem(dev);
+ if (ctlr->r_mem != NULL)
+ bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
+ ctlr->r_mem);
}
return error;
}
static int
-ahci_pci_detach(device_t dev)
+ahci_gen_detach(device_t dev)
{
ahci_detach(dev);
- pci_release_msi(dev);
return (0);
}
-static int
-ahci_pci_suspend(device_t dev)
-{
- struct ahci_controller *ctlr = device_get_softc(dev);
-
- bus_generic_suspend(dev);
- /* Disable interupts, so the state change(s) doesn't trigger */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC,
- ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
- return 0;
-}
-
-static int
-ahci_pci_resume(device_t dev)
-{
- int res;
-
- if ((res = ahci_pci_ctlr_reset(dev)) != 0)
- return (res);
- ahci_ctlr_setup(dev);
- return (bus_generic_resume(dev));
-}
-
-devclass_t ahci_devclass;
+static devclass_t ahci_gen_devclass;
static device_method_t ahci_methods[] = {
DEVMETHOD(device_probe, ahci_probe),
- DEVMETHOD(device_attach, ahci_pci_attach),
- DEVMETHOD(device_detach, ahci_pci_detach),
- DEVMETHOD(device_suspend, ahci_pci_suspend),
- DEVMETHOD(device_resume, ahci_pci_resume),
+ DEVMETHOD(device_attach, ahci_gen_attach),
+ DEVMETHOD(device_detach, ahci_gen_detach),
DEVMETHOD(bus_print_child, ahci_print_child),
DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
DEVMETHOD(bus_release_resource, ahci_release_resource),
@@ -600,28 +124,8 @@ static device_method_t ahci_methods[] =
DEVMETHOD_END
};
static driver_t ahci_driver = {
- "ahci",
- ahci_methods,
- sizeof(struct ahci_controller)
-};
-DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL);
-static device_method_t ahci_ata_methods[] = {
- DEVMETHOD(device_probe, ahci_ata_probe),
- DEVMETHOD(device_attach, ahci_pci_attach),
- DEVMETHOD(device_detach, ahci_pci_detach),
- DEVMETHOD(device_suspend, ahci_pci_suspend),
- DEVMETHOD(device_resume, ahci_pci_resume),
- DEVMETHOD(bus_print_child, ahci_print_child),
- DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
- DEVMETHOD(bus_release_resource, ahci_release_resource),
- DEVMETHOD(bus_setup_intr, ahci_setup_intr),
- DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
- DEVMETHOD(bus_child_location_str, ahci_child_location_str),
- DEVMETHOD_END
-};
-static driver_t ahci_ata_driver = {
- "ahci",
- ahci_ata_methods,
- sizeof(struct ahci_controller)
+ "ahci",
+ ahci_methods,
+ sizeof(struct ahci_controller)
};
-DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, NULL, NULL);
+DRIVER_MODULE(ahci, simplebus, ahci_driver, ahci_gen_devclass, NULL, NULL);
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