svn commit: r247625 - stable/9/contrib/llvm/lib/Target/X86

[Dimitry Andric]

Author: dim
Date: Sat Mar  2 14:39:48 2013
New Revision: 247625
URL: http://svnweb.freebsd.org/changeset/base/247625

Log:
  MFC r247205:
  
  Pull in r175962 from upstream llvm trunk:
  
    X86: Disable cmov-memory patterns on subtargets without cmov.
  
    Fixes PR15115.
  
  For the i386 arch, this should enable cmov instructions only on
  -march=pentiumpro and higher.  Since our default CPU is i486, cmov
  instructions will now be disabled by default.

Modified:
  stable/9/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
Directory Properties:
  stable/9/contrib/llvm/   (props changed)

Modified: stable/9/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
==============================================================================
--- stable/9/contrib/llvm/lib/Target/X86/X86InstrCompiler.td	Sat Mar  2 14:35:15 2013	(r247624)
+++ stable/9/contrib/llvm/lib/Target/X86/X86InstrCompiler.td	Sat Mar  2 14:39:48 2013	(r247625)
@@ -1076,12 +1076,14 @@ def : Pat<(X86cmp GR64:$src1, 0),
 // inverted.
 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
                   Instruction Inst64> {
-  def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
-            (Inst16 GR16:$src2, addr:$src1)>;
-  def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
-            (Inst32 GR32:$src2, addr:$src1)>;
-  def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
-            (Inst64 GR64:$src2, addr:$src1)>;
+  let Predicates = [HasCMov] in {
+    def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
+              (Inst16 GR16:$src2, addr:$src1)>;
+    def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
+              (Inst32 GR32:$src2, addr:$src1)>;
+    def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
+              (Inst64 GR64:$src2, addr:$src1)>;
+  }
 }
 
 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;