svn commit: r245877 - head/sys/mips/nlm
Jayachandran C.
jchandra at FreeBSD.org
Thu Jan 24 11:42:16 UTC 2013
Author: jchandra
Date: Thu Jan 24 11:42:16 2013
New Revision: 245877
URL: http://svnweb.freebsd.org/changeset/base/245877
Log:
Little-endian fix for PCI on Broadcom XLP.
Update the function xlp_pcib_hardware_swap_enable() to do nothing
when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred
in little-endian mode as the endianness matches that of CPU.
Modified:
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/xlp_pci.c
==============================================================================
--- head/sys/mips/nlm/xlp_pci.c Thu Jan 24 09:36:50 2013 (r245876)
+++ head/sys/mips/nlm/xlp_pci.c Thu Jan 24 11:42:16 2013 (r245877)
@@ -487,12 +487,14 @@ xlp_pcib_write_config(device_t dev, u_in
}
/*
- * Enable byte swap in hardware. Program a link's PCIe SWAP regions
- * from the link's IO and MEM address ranges.
+ * Enable byte swap in hardware when compiled big-endian.
+ * Programs a link's PCIe SWAP regions from the link's IO and MEM address
+ * ranges.
*/
static void
xlp_pcib_hardware_swap_enable(int node, int link)
{
+#if BYTE_ORDER == BIG_ENDIAN
uint64_t bbase, linkpcibase;
uint32_t bar;
int pcieoffset;
@@ -514,6 +516,7 @@ xlp_pcib_hardware_swap_enable(int node,
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
+#endif
}
static int
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