svn commit: r232809 - in vendor-sys/octeon-sdk/dist: . cvmx-malloc
libfdt
Juli Mallett
jmallett at FreeBSD.org
Sun Mar 11 04:14:01 UTC 2012
Author: jmallett
Date: Sun Mar 11 04:14:00 2012
New Revision: 232809
URL: http://svn.freebsd.org/changeset/base/232809
Log:
Import Cavium Octeon SDK 2.3.0 Simple Executive from cnusers.org.
Added:
vendor-sys/octeon-sdk/dist/README.txt
vendor-sys/octeon-sdk/dist/cvmx-ciu2-defs.h
vendor-sys/octeon-sdk/dist/cvmx-endor-defs.h
vendor-sys/octeon-sdk/dist/cvmx-eoi-defs.h
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn61xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn66xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn68xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn68xxp1.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cnf71xx.c
vendor-sys/octeon-sdk/dist/cvmx-helper-cfg.c
vendor-sys/octeon-sdk/dist/cvmx-helper-cfg.h
vendor-sys/octeon-sdk/dist/cvmx-helper-ilk.c
vendor-sys/octeon-sdk/dist/cvmx-helper-ilk.h
vendor-sys/octeon-sdk/dist/cvmx-hfa.c
vendor-sys/octeon-sdk/dist/cvmx-hfa.h
vendor-sys/octeon-sdk/dist/cvmx-ilk-defs.h
vendor-sys/octeon-sdk/dist/cvmx-ilk.c
vendor-sys/octeon-sdk/dist/cvmx-ilk.h
vendor-sys/octeon-sdk/dist/cvmx-iob1-defs.h
vendor-sys/octeon-sdk/dist/cvmx-ipd.c
vendor-sys/octeon-sdk/dist/cvmx-malloc/
vendor-sys/octeon-sdk/dist/cvmx-malloc/README-malloc
vendor-sys/octeon-sdk/dist/cvmx-malloc/arena.c
vendor-sys/octeon-sdk/dist/cvmx-malloc/malloc.c
vendor-sys/octeon-sdk/dist/cvmx-malloc/malloc.h
vendor-sys/octeon-sdk/dist/cvmx-malloc/thread-m.h
vendor-sys/octeon-sdk/dist/cvmx-profiler.c
vendor-sys/octeon-sdk/dist/cvmx-profiler.h
vendor-sys/octeon-sdk/dist/cvmx-qlm-tables.c
vendor-sys/octeon-sdk/dist/cvmx-qlm.c
vendor-sys/octeon-sdk/dist/cvmx-qlm.h
vendor-sys/octeon-sdk/dist/cvmx-resources.config
vendor-sys/octeon-sdk/dist/cvmx-shared-linux-n32.ld
vendor-sys/octeon-sdk/dist/cvmx-shared-linux-o32.ld
vendor-sys/octeon-sdk/dist/cvmx-shared-linux.ld
vendor-sys/octeon-sdk/dist/cvmx-sso-defs.h
vendor-sys/octeon-sdk/dist/cvmx-trax-defs.h
vendor-sys/octeon-sdk/dist/cvmx.mk
vendor-sys/octeon-sdk/dist/executive-config.h.template
vendor-sys/octeon-sdk/dist/libfdt/
vendor-sys/octeon-sdk/dist/libfdt/fdt.c
vendor-sys/octeon-sdk/dist/libfdt/fdt.h
vendor-sys/octeon-sdk/dist/libfdt/fdt_ro.c
vendor-sys/octeon-sdk/dist/libfdt/fdt_rw.c
vendor-sys/octeon-sdk/dist/libfdt/fdt_strerror.c
vendor-sys/octeon-sdk/dist/libfdt/fdt_sw.c
vendor-sys/octeon-sdk/dist/libfdt/fdt_wip.c
vendor-sys/octeon-sdk/dist/libfdt/libfdt.h
vendor-sys/octeon-sdk/dist/libfdt/libfdt.mk
vendor-sys/octeon-sdk/dist/libfdt/libfdt_env.h
vendor-sys/octeon-sdk/dist/libfdt/libfdt_internal.h
vendor-sys/octeon-sdk/dist/octeon-feature.c
Modified:
vendor-sys/octeon-sdk/dist/cvmip.h
vendor-sys/octeon-sdk/dist/cvmx-abi.h
vendor-sys/octeon-sdk/dist/cvmx-access-native.h
vendor-sys/octeon-sdk/dist/cvmx-access.h
vendor-sys/octeon-sdk/dist/cvmx-address.h
vendor-sys/octeon-sdk/dist/cvmx-agl-defs.h
vendor-sys/octeon-sdk/dist/cvmx-app-hotplug.c
vendor-sys/octeon-sdk/dist/cvmx-app-hotplug.h
vendor-sys/octeon-sdk/dist/cvmx-app-init-linux.c
vendor-sys/octeon-sdk/dist/cvmx-app-init.c
vendor-sys/octeon-sdk/dist/cvmx-app-init.h
vendor-sys/octeon-sdk/dist/cvmx-asm.h
vendor-sys/octeon-sdk/dist/cvmx-asx0-defs.h
vendor-sys/octeon-sdk/dist/cvmx-asxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-atomic.h
vendor-sys/octeon-sdk/dist/cvmx-bootloader.h
vendor-sys/octeon-sdk/dist/cvmx-bootmem.c
vendor-sys/octeon-sdk/dist/cvmx-bootmem.h
vendor-sys/octeon-sdk/dist/cvmx-ciu-defs.h
vendor-sys/octeon-sdk/dist/cvmx-clock.c
vendor-sys/octeon-sdk/dist/cvmx-clock.h
vendor-sys/octeon-sdk/dist/cvmx-cmd-queue.c
vendor-sys/octeon-sdk/dist/cvmx-cmd-queue.h
vendor-sys/octeon-sdk/dist/cvmx-cn3010-evb-hs5.c
vendor-sys/octeon-sdk/dist/cvmx-cn3010-evb-hs5.h
vendor-sys/octeon-sdk/dist/cvmx-compactflash.c
vendor-sys/octeon-sdk/dist/cvmx-compactflash.h
vendor-sys/octeon-sdk/dist/cvmx-core.c
vendor-sys/octeon-sdk/dist/cvmx-core.h
vendor-sys/octeon-sdk/dist/cvmx-coremask.c
vendor-sys/octeon-sdk/dist/cvmx-coremask.h
vendor-sys/octeon-sdk/dist/cvmx-crypto.c
vendor-sys/octeon-sdk/dist/cvmx-crypto.h
vendor-sys/octeon-sdk/dist/cvmx-csr-db-support.c
vendor-sys/octeon-sdk/dist/cvmx-csr-db.c
vendor-sys/octeon-sdk/dist/cvmx-csr-db.h
vendor-sys/octeon-sdk/dist/cvmx-csr-enums.h
vendor-sys/octeon-sdk/dist/cvmx-csr-typedefs.h
vendor-sys/octeon-sdk/dist/cvmx-csr.h
vendor-sys/octeon-sdk/dist/cvmx-dbg-defs.h
vendor-sys/octeon-sdk/dist/cvmx-debug-handler.S
vendor-sys/octeon-sdk/dist/cvmx-debug-remote.c
vendor-sys/octeon-sdk/dist/cvmx-debug-uart.c
vendor-sys/octeon-sdk/dist/cvmx-debug.c
vendor-sys/octeon-sdk/dist/cvmx-debug.h
vendor-sys/octeon-sdk/dist/cvmx-dfa-defs.h
vendor-sys/octeon-sdk/dist/cvmx-dfa.c
vendor-sys/octeon-sdk/dist/cvmx-dfa.h
vendor-sys/octeon-sdk/dist/cvmx-dfm-defs.h
vendor-sys/octeon-sdk/dist/cvmx-dma-engine.c
vendor-sys/octeon-sdk/dist/cvmx-dma-engine.h
vendor-sys/octeon-sdk/dist/cvmx-dpi-defs.h
vendor-sys/octeon-sdk/dist/cvmx-ebt3000.c
vendor-sys/octeon-sdk/dist/cvmx-ebt3000.h
vendor-sys/octeon-sdk/dist/cvmx-error-custom.c
vendor-sys/octeon-sdk/dist/cvmx-error-custom.h
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn30xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn31xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn38xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn38xxp2.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn50xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn52xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn52xxp1.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn56xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn56xxp1.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn58xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn58xxp1.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn63xx.c
vendor-sys/octeon-sdk/dist/cvmx-error-init-cn63xxp1.c
vendor-sys/octeon-sdk/dist/cvmx-error.c
vendor-sys/octeon-sdk/dist/cvmx-error.h
vendor-sys/octeon-sdk/dist/cvmx-fau.h
vendor-sys/octeon-sdk/dist/cvmx-flash.c
vendor-sys/octeon-sdk/dist/cvmx-flash.h
vendor-sys/octeon-sdk/dist/cvmx-fpa-defs.h
vendor-sys/octeon-sdk/dist/cvmx-fpa.c
vendor-sys/octeon-sdk/dist/cvmx-fpa.h
vendor-sys/octeon-sdk/dist/cvmx-gmx.h
vendor-sys/octeon-sdk/dist/cvmx-gmxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-gpio-defs.h
vendor-sys/octeon-sdk/dist/cvmx-gpio.h
vendor-sys/octeon-sdk/dist/cvmx-helper-board.c
vendor-sys/octeon-sdk/dist/cvmx-helper-board.h
vendor-sys/octeon-sdk/dist/cvmx-helper-check-defines.h
vendor-sys/octeon-sdk/dist/cvmx-helper-errata.c
vendor-sys/octeon-sdk/dist/cvmx-helper-errata.h
vendor-sys/octeon-sdk/dist/cvmx-helper-fpa.c
vendor-sys/octeon-sdk/dist/cvmx-helper-fpa.h
vendor-sys/octeon-sdk/dist/cvmx-helper-jtag.c
vendor-sys/octeon-sdk/dist/cvmx-helper-jtag.h
vendor-sys/octeon-sdk/dist/cvmx-helper-loop.c
vendor-sys/octeon-sdk/dist/cvmx-helper-loop.h
vendor-sys/octeon-sdk/dist/cvmx-helper-npi.c
vendor-sys/octeon-sdk/dist/cvmx-helper-npi.h
vendor-sys/octeon-sdk/dist/cvmx-helper-rgmii.c
vendor-sys/octeon-sdk/dist/cvmx-helper-rgmii.h
vendor-sys/octeon-sdk/dist/cvmx-helper-sgmii.c
vendor-sys/octeon-sdk/dist/cvmx-helper-sgmii.h
vendor-sys/octeon-sdk/dist/cvmx-helper-spi.c
vendor-sys/octeon-sdk/dist/cvmx-helper-spi.h
vendor-sys/octeon-sdk/dist/cvmx-helper-srio.c
vendor-sys/octeon-sdk/dist/cvmx-helper-srio.h
vendor-sys/octeon-sdk/dist/cvmx-helper-util.c
vendor-sys/octeon-sdk/dist/cvmx-helper-util.h
vendor-sys/octeon-sdk/dist/cvmx-helper-xaui.c
vendor-sys/octeon-sdk/dist/cvmx-helper-xaui.h
vendor-sys/octeon-sdk/dist/cvmx-helper.c
vendor-sys/octeon-sdk/dist/cvmx-helper.h
vendor-sys/octeon-sdk/dist/cvmx-higig.h
vendor-sys/octeon-sdk/dist/cvmx-interrupt-handler.S
vendor-sys/octeon-sdk/dist/cvmx-interrupt.c
vendor-sys/octeon-sdk/dist/cvmx-interrupt.h
vendor-sys/octeon-sdk/dist/cvmx-iob-defs.h
vendor-sys/octeon-sdk/dist/cvmx-ipd-defs.h
vendor-sys/octeon-sdk/dist/cvmx-ipd.h
vendor-sys/octeon-sdk/dist/cvmx-ixf18201.c
vendor-sys/octeon-sdk/dist/cvmx-ixf18201.h
vendor-sys/octeon-sdk/dist/cvmx-key-defs.h
vendor-sys/octeon-sdk/dist/cvmx-key.h
vendor-sys/octeon-sdk/dist/cvmx-l2c-defs.h
vendor-sys/octeon-sdk/dist/cvmx-l2c.c
vendor-sys/octeon-sdk/dist/cvmx-l2c.h
vendor-sys/octeon-sdk/dist/cvmx-l2d-defs.h
vendor-sys/octeon-sdk/dist/cvmx-l2t-defs.h
vendor-sys/octeon-sdk/dist/cvmx-led-defs.h
vendor-sys/octeon-sdk/dist/cvmx-llm.c
vendor-sys/octeon-sdk/dist/cvmx-llm.h
vendor-sys/octeon-sdk/dist/cvmx-lmcx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-log-arc.S
vendor-sys/octeon-sdk/dist/cvmx-log.c
vendor-sys/octeon-sdk/dist/cvmx-log.h
vendor-sys/octeon-sdk/dist/cvmx-malloc.h
vendor-sys/octeon-sdk/dist/cvmx-mdio.h
vendor-sys/octeon-sdk/dist/cvmx-mgmt-port.c
vendor-sys/octeon-sdk/dist/cvmx-mgmt-port.h
vendor-sys/octeon-sdk/dist/cvmx-mio-defs.h
vendor-sys/octeon-sdk/dist/cvmx-mixx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-mpi-defs.h
vendor-sys/octeon-sdk/dist/cvmx-nand.c
vendor-sys/octeon-sdk/dist/cvmx-nand.h
vendor-sys/octeon-sdk/dist/cvmx-ndf-defs.h
vendor-sys/octeon-sdk/dist/cvmx-npei-defs.h
vendor-sys/octeon-sdk/dist/cvmx-npi-defs.h
vendor-sys/octeon-sdk/dist/cvmx-npi.h
vendor-sys/octeon-sdk/dist/cvmx-packet.h
vendor-sys/octeon-sdk/dist/cvmx-pci-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pci.h
vendor-sys/octeon-sdk/dist/cvmx-pcie.c
vendor-sys/octeon-sdk/dist/cvmx-pcie.h
vendor-sys/octeon-sdk/dist/cvmx-pcieepx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pciercx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pcm-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pcmx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pcsx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pcsxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pemx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pescx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pexp-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pip-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pip.h
vendor-sys/octeon-sdk/dist/cvmx-pko-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pko.c
vendor-sys/octeon-sdk/dist/cvmx-pko.h
vendor-sys/octeon-sdk/dist/cvmx-platform.h
vendor-sys/octeon-sdk/dist/cvmx-pow-defs.h
vendor-sys/octeon-sdk/dist/cvmx-pow.c
vendor-sys/octeon-sdk/dist/cvmx-pow.h
vendor-sys/octeon-sdk/dist/cvmx-power-throttle.c
vendor-sys/octeon-sdk/dist/cvmx-power-throttle.h
vendor-sys/octeon-sdk/dist/cvmx-rad-defs.h
vendor-sys/octeon-sdk/dist/cvmx-raid.c
vendor-sys/octeon-sdk/dist/cvmx-raid.h
vendor-sys/octeon-sdk/dist/cvmx-rng.h
vendor-sys/octeon-sdk/dist/cvmx-rnm-defs.h
vendor-sys/octeon-sdk/dist/cvmx-rtc.h
vendor-sys/octeon-sdk/dist/cvmx-rwlock.h
vendor-sys/octeon-sdk/dist/cvmx-scratch.h
vendor-sys/octeon-sdk/dist/cvmx-shmem.c
vendor-sys/octeon-sdk/dist/cvmx-shmem.h
vendor-sys/octeon-sdk/dist/cvmx-sim-magic.h
vendor-sys/octeon-sdk/dist/cvmx-sli-defs.h
vendor-sys/octeon-sdk/dist/cvmx-smi-defs.h
vendor-sys/octeon-sdk/dist/cvmx-smix-defs.h
vendor-sys/octeon-sdk/dist/cvmx-spi.c
vendor-sys/octeon-sdk/dist/cvmx-spi.h
vendor-sys/octeon-sdk/dist/cvmx-spi4000.c
vendor-sys/octeon-sdk/dist/cvmx-spinlock.h
vendor-sys/octeon-sdk/dist/cvmx-spx0-defs.h
vendor-sys/octeon-sdk/dist/cvmx-spxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-srio.c
vendor-sys/octeon-sdk/dist/cvmx-srio.h
vendor-sys/octeon-sdk/dist/cvmx-sriomaintx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-sriox-defs.h
vendor-sys/octeon-sdk/dist/cvmx-srxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-stxx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-swap.h
vendor-sys/octeon-sdk/dist/cvmx-sysinfo.c
vendor-sys/octeon-sdk/dist/cvmx-sysinfo.h
vendor-sys/octeon-sdk/dist/cvmx-thunder.c
vendor-sys/octeon-sdk/dist/cvmx-thunder.h
vendor-sys/octeon-sdk/dist/cvmx-tim-defs.h
vendor-sys/octeon-sdk/dist/cvmx-tim.c
vendor-sys/octeon-sdk/dist/cvmx-tim.h
vendor-sys/octeon-sdk/dist/cvmx-tlb.c
vendor-sys/octeon-sdk/dist/cvmx-tlb.h
vendor-sys/octeon-sdk/dist/cvmx-tra-defs.h
vendor-sys/octeon-sdk/dist/cvmx-tra.c
vendor-sys/octeon-sdk/dist/cvmx-tra.h
vendor-sys/octeon-sdk/dist/cvmx-twsi.c
vendor-sys/octeon-sdk/dist/cvmx-twsi.h
vendor-sys/octeon-sdk/dist/cvmx-uahcx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-uart.c
vendor-sys/octeon-sdk/dist/cvmx-uart.h
vendor-sys/octeon-sdk/dist/cvmx-uctlx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-usb.c
vendor-sys/octeon-sdk/dist/cvmx-usb.h
vendor-sys/octeon-sdk/dist/cvmx-usbcx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-usbd.c
vendor-sys/octeon-sdk/dist/cvmx-usbd.h
vendor-sys/octeon-sdk/dist/cvmx-usbnx-defs.h
vendor-sys/octeon-sdk/dist/cvmx-utils.h
vendor-sys/octeon-sdk/dist/cvmx-version.h
vendor-sys/octeon-sdk/dist/cvmx-warn.c
vendor-sys/octeon-sdk/dist/cvmx-warn.h
vendor-sys/octeon-sdk/dist/cvmx-wqe.h
vendor-sys/octeon-sdk/dist/cvmx-zip-defs.h
vendor-sys/octeon-sdk/dist/cvmx-zip.c
vendor-sys/octeon-sdk/dist/cvmx-zip.h
vendor-sys/octeon-sdk/dist/cvmx-zone.c
vendor-sys/octeon-sdk/dist/cvmx.h
vendor-sys/octeon-sdk/dist/octeon-boot-info.h
vendor-sys/octeon-sdk/dist/octeon-feature.h
vendor-sys/octeon-sdk/dist/octeon-model.c
vendor-sys/octeon-sdk/dist/octeon-model.h
vendor-sys/octeon-sdk/dist/octeon-pci-console.c
vendor-sys/octeon-sdk/dist/octeon-pci-console.h
Added: vendor-sys/octeon-sdk/dist/README.txt
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor-sys/octeon-sdk/dist/README.txt Sun Mar 11 04:14:00 2012 (r232809)
@@ -0,0 +1,43 @@
+Readme for the OCTEON Executive Library
+
+
+The OCTEON Executive Library provides runtime support and hardware
+abstraction for the OCTEON processor. The executive is composed of the
+libcvmx.a library as well as header files that provide
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the
+HTML documentation for more information on the build system.)
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in
+the local obj directory. Each file using the executive
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the
+executive and is generated by the cvmx-config script from an
+'executive-config.h' file. A sample version of this file is provided
+in the executive directory as 'executive-config.h.template'.
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory
+of the application directory and customize as required by the application.
+Applications that don't use any simple executive functionality can omit
+the cvmx-config.h header file. Please refer to the examples for a
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.
Modified: vendor-sys/octeon-sdk/dist/cvmip.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmip.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmip.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,11 @@
/**
* @file
*
- * Cavium Networks Internet Protocol (IP)
+ * Cavium Inc. Internet Protocol (IP)
*
* Definitions for the Internet Protocol (IP) support.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*/
Modified: vendor-sys/octeon-sdk/dist/cvmx-abi.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmx-abi.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmx-abi.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -39,21 +39,21 @@
-
-
-
-
/**
* @file
*
* This file defines macros for use in determining the current calling ABI.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*/
#ifndef __CVMX_ABI_H__
#define __CVMX_ABI_H__
+#ifndef __U_BOOT__
+#include <endian.h>
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -87,6 +87,20 @@ extern "C" {
#endif
#endif
+/* For compatibility with Linux definitions... */
+#if __BYTE_ORDER == __BIG_ENDIAN
+# ifndef __BIG_ENDIAN_BITFIELD
+# define __BIG_ENDIAN_BITFIELD
+# endif
+#else
+# ifndef __LITTLE_ENDIAN_BITFIELD
+# define __LITTLE_ENDIAN_BITFIELD
+# endif
+#endif
+#if defined(__BIG_ENDIAN_BITFIELD) && defined(__LITTLE_ENDIAN_BITFIELD)
+# error Cannot define both __BIG_ENDIAN_BITFIELD and __LITTLE_ENDIAN_BITFIELD
+#endif
+
#ifdef __cplusplus
}
#endif
Modified: vendor-sys/octeon-sdk/dist/cvmx-access-native.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmx-access-native.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmx-access-native.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -181,12 +181,6 @@ static inline void *cvmx_phys_to_ptr(uin
cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
#ifdef CVMX_BUILD_FOR_UBOOT
-#if !CONFIG_OCTEON_UBOOT_TLB
- if (physical_address >= 0x80000000)
- return NULL;
- else
- return CASTPTR(void, (physical_address & 0x7FFFFFFF));
-#endif
/* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
** which can have a physical address above the 32 bit address space. 1-1 mappings are used
@@ -249,8 +243,9 @@ static inline void *cvmx_phys_to_ptr(uin
2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
- else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
- (physical_address < 0x420000000ull))
+ else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+ && (physical_address >= 0x410000000ull)
+ && (physical_address < 0x420000000ull))
return CASTPTR(void, physical_address - 0x400000000ull);
else
return CASTPTR(void, physical_address);
Modified: vendor-sys/octeon-sdk/dist/cvmx-access.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmx-access.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmx-access.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
Modified: vendor-sys/octeon-sdk/dist/cvmx-address.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmx-address.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmx-address.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,10 @@
#ifndef __CVMX_ADDRESS_H__
#define __CVMX_ADDRESS_H__
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-abi.h"
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -233,6 +237,7 @@ typedef union {
#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
@@ -245,6 +250,14 @@ typedef union {
#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_ABI_N32
+#define UNMAPPED_PTR(x) ( (1U << 31) | x )
+#else
+#define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
+#endif
+#endif
+
#ifdef __cplusplus
}
#endif
Modified: vendor-sys/octeon-sdk/dist/cvmx-agl-defs.h
==============================================================================
--- vendor-sys/octeon-sdk/dist/cvmx-agl-defs.h Sun Mar 11 04:12:59 2012 (r232808)
+++ vendor-sys/octeon-sdk/dist/cvmx-agl-defs.h Sun Mar 11 04:14:00 2012 (r232809)
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support at cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_AGL_TYPEDEFS_H__
-#define __CVMX_AGL_TYPEDEFS_H__
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
}
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_AGL_GMX_BAD_
#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
}
@@ -102,7 +102,10 @@ static inline uint64_t CVMX_AGL_GMX_PRTX
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
}
@@ -115,7 +118,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048;
}
@@ -128,7 +134,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048;
}
@@ -141,7 +150,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048;
}
@@ -154,7 +166,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048;
}
@@ -167,7 +182,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048;
}
@@ -180,7 +198,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048;
}
@@ -193,7 +214,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048;
}
@@ -206,7 +230,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048;
}
@@ -219,7 +246,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048;
}
@@ -232,7 +262,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048;
}
@@ -245,7 +278,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048;
}
@@ -258,7 +294,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048;
}
@@ -271,7 +310,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048;
}
@@ -284,7 +326,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048;
}
@@ -297,7 +342,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048;
}
@@ -310,7 +358,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048;
}
@@ -323,7 +374,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048;
}
@@ -336,7 +390,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048;
}
@@ -347,7 +404,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
static inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048;
}
@@ -360,7 +420,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048;
}
@@ -373,7 +436,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048;
}
@@ -386,7 +452,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048;
}
@@ -399,7 +468,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048;
}
@@ -412,7 +484,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048;
}
@@ -425,7 +500,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048;
}
@@ -438,7 +516,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048;
}
@@ -451,7 +532,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048;
}
@@ -464,7 +548,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048;
}
@@ -477,7 +564,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048;
}
@@ -490,7 +580,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048;
}
@@ -503,7 +596,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8;
}
@@ -516,7 +612,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8;
}
@@ -529,7 +628,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8;
}
@@ -540,7 +642,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_B
#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
}
@@ -551,7 +653,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_P
#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
}
@@ -564,7 +666,10 @@ static inline uint64_t CVMX_AGL_GMX_SMAC
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048;
}
@@ -575,7 +680,7 @@ static inline uint64_t CVMX_AGL_GMX_SMAC
#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
}
@@ -588,7 +693,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048;
}
@@ -599,7 +707,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
static inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048;
}
@@ -612,7 +723,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048;
}
@@ -625,7 +739,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048;
}
@@ -638,7 +755,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048;
}
@@ -651,7 +771,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048;
}
@@ -664,7 +787,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048;
}
@@ -677,7 +803,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048;
}
@@ -690,7 +819,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048;
}
@@ -703,7 +835,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048;
}
@@ -716,7 +851,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048;
}
@@ -729,7 +867,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048;
}
@@ -742,7 +883,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048;
}
@@ -755,7 +899,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048;
}
@@ -768,7 +915,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048;
}
@@ -781,7 +931,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048;
}
@@ -794,7 +947,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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