svn commit: r227722 - head/sys/mips/nlm/hal
Jayachandran C.
jchandra at FreeBSD.org
Sat Nov 19 14:06:15 UTC 2011
Author: jchandra
Date: Sat Nov 19 14:06:15 2011
New Revision: 227722
URL: http://svn.freebsd.org/changeset/base/227722
Log:
Whitespace fixes in XLP HAL files.
Also fixup a macro in iomap.h
Modified:
head/sys/mips/nlm/hal/bridge.h
head/sys/mips/nlm/hal/cop2.h
head/sys/mips/nlm/hal/cpucontrol.h
head/sys/mips/nlm/hal/haldefs.h
head/sys/mips/nlm/hal/iomap.h
head/sys/mips/nlm/hal/mips-extns.h
head/sys/mips/nlm/hal/mmu.h
head/sys/mips/nlm/hal/pcibus.h
head/sys/mips/nlm/hal/uart.h
Modified: head/sys/mips/nlm/hal/bridge.h
==============================================================================
--- head/sys/mips/nlm/hal/bridge.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/bridge.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,7 +30,7 @@
*/
#ifndef __NLM_HAL_BRIDGE_H__
-#define __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
/**
* @file_name mio.h
@@ -44,141 +44,141 @@
* These registers start after the PCIe header, which has 0x40
* standard entries
*/
-#define BRIDGE_MODE 0x00
-#define BRIDGE_PCI_CFG_BASE 0x01
-#define BRIDGE_PCI_CFG_LIMIT 0x02
-#define BRIDGE_PCIE_CFG_BASE 0x03
-#define BRIDGE_PCIE_CFG_LIMIT 0x04
-#define BRIDGE_BUSNUM_BAR0 0x05
-#define BRIDGE_BUSNUM_BAR1 0x06
-#define BRIDGE_BUSNUM_BAR2 0x07
-#define BRIDGE_BUSNUM_BAR3 0x08
-#define BRIDGE_BUSNUM_BAR4 0x09
-#define BRIDGE_BUSNUM_BAR5 0x0a
-#define BRIDGE_BUSNUM_BAR6 0x0b
-#define BRIDGE_FLASH_BAR0 0x0c
-#define BRIDGE_FLASH_BAR1 0x0d
-#define BRIDGE_FLASH_BAR2 0x0e
-#define BRIDGE_FLASH_BAR3 0x0f
-#define BRIDGE_FLASH_LIMIT0 0x10
-#define BRIDGE_FLASH_LIMIT1 0x11
-#define BRIDGE_FLASH_LIMIT2 0x12
-#define BRIDGE_FLASH_LIMIT3 0x13
-
-#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
-#define BRIDGE_DRAM_BAR0 0x14
-#define BRIDGE_DRAM_BAR1 0x15
-#define BRIDGE_DRAM_BAR2 0x16
-#define BRIDGE_DRAM_BAR3 0x17
-#define BRIDGE_DRAM_BAR4 0x18
-#define BRIDGE_DRAM_BAR5 0x19
-#define BRIDGE_DRAM_BAR6 0x1a
-#define BRIDGE_DRAM_BAR7 0x1b
-
-#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
-#define BRIDGE_DRAM_LIMIT0 0x1c
-#define BRIDGE_DRAM_LIMIT1 0x1d
-#define BRIDGE_DRAM_LIMIT2 0x1e
-#define BRIDGE_DRAM_LIMIT3 0x1f
-#define BRIDGE_DRAM_LIMIT4 0x20
-#define BRIDGE_DRAM_LIMIT5 0x21
-#define BRIDGE_DRAM_LIMIT6 0x22
-#define BRIDGE_DRAM_LIMIT7 0x23
-
-#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
-#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
-#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
-#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
-#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
-#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
-#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
-#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
-#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
-#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
-#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
-#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
-#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
-#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
-#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
-#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
-#define BRIDGE_PCIEMEM_BASE0 0x34
-#define BRIDGE_PCIEMEM_BASE1 0x35
-#define BRIDGE_PCIEMEM_BASE2 0x36
-#define BRIDGE_PCIEMEM_BASE3 0x37
-#define BRIDGE_PCIEMEM_LIMIT0 0x38
-#define BRIDGE_PCIEMEM_LIMIT1 0x39
-#define BRIDGE_PCIEMEM_LIMIT2 0x3a
-#define BRIDGE_PCIEMEM_LIMIT3 0x3b
-#define BRIDGE_PCIEIO_BASE0 0x3c
-#define BRIDGE_PCIEIO_BASE1 0x3d
-#define BRIDGE_PCIEIO_BASE2 0x3e
-#define BRIDGE_PCIEIO_BASE3 0x3f
-#define BRIDGE_PCIEIO_LIMIT0 0x40
-#define BRIDGE_PCIEIO_LIMIT1 0x41
-#define BRIDGE_PCIEIO_LIMIT2 0x42
-#define BRIDGE_PCIEIO_LIMIT3 0x43
-#define BRIDGE_PCIEMEM_BASE4 0x44
-#define BRIDGE_PCIEMEM_BASE5 0x45
-#define BRIDGE_PCIEMEM_BASE6 0x46
-#define BRIDGE_PCIEMEM_LIMIT4 0x47
-#define BRIDGE_PCIEMEM_LIMIT5 0x48
-#define BRIDGE_PCIEMEM_LIMIT6 0x49
-#define BRIDGE_PCIEIO_BASE4 0x4a
-#define BRIDGE_PCIEIO_BASE5 0x4b
-#define BRIDGE_PCIEIO_BASE6 0x4c
-#define BRIDGE_PCIEIO_LIMIT4 0x4d
-#define BRIDGE_PCIEIO_LIMIT5 0x4e
-#define BRIDGE_PCIEIO_LIMIT6 0x4f
-#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
-#define BRIDGE_EVNTCTR1_LOW 0x51
-#define BRIDGE_EVNTCTR1_HI 0x52
-#define BRIDGE_EVNT_CNT_CTL2 0x53
-#define BRIDGE_EVNTCTR2_LOW 0x54
-#define BRIDGE_EVNTCTR2_HI 0x55
-#define BRIDGE_TRACEBUF_MATCH0 0x56
-#define BRIDGE_TRACEBUF_MATCH1 0x57
-#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
-#define BRIDGE_TRACEBUF_MATCH_HI 0x59
-#define BRIDGE_TRACEBUF_CTRL 0x5a
-#define BRIDGE_TRACEBUF_INIT 0x5b
-#define BRIDGE_TRACEBUF_ACCESS 0x5c
-#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
-#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
-#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
-#define BRIDGE_TRACEBUF_READ_DATA3 0x60
-#define BRIDGE_TRACEBUF_STATUS 0x61
-#define BRIDGE_ADDRESS_ERROR0 0x62
-#define BRIDGE_ADDRESS_ERROR1 0x63
-#define BRIDGE_ADDRESS_ERROR2 0x64
-#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
-#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
-#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
-#define BRIDGE_LINE_FLUSH0 0x68
-#define BRIDGE_LINE_FLUSH1 0x69
-#define BRIDGE_NODE_ID 0x6a
-#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
-#define BRIDGE_PCIE0_WEIGHT 0x2c0
-#define BRIDGE_PCIE1_WEIGHT 0x2c1
-#define BRIDGE_PCIE2_WEIGHT 0x2c2
-#define BRIDGE_PCIE3_WEIGHT 0x2c3
-#define BRIDGE_USB_WEIGHT 0x2c4
-#define BRIDGE_NET_WEIGHT 0x2c5
-#define BRIDGE_POE_WEIGHT 0x2c6
-#define BRIDGE_CMS_WEIGHT 0x2c7
-#define BRIDGE_DMAENG_WEIGHT 0x2c8
-#define BRIDGE_SEC_WEIGHT 0x2c9
-#define BRIDGE_COMP_WEIGHT 0x2ca
-#define BRIDGE_GIO_WEIGHT 0x2cb
-#define BRIDGE_FLASH_WEIGHT 0x2cc
+#define BRIDGE_MODE 0x00
+#define BRIDGE_PCI_CFG_BASE 0x01
+#define BRIDGE_PCI_CFG_LIMIT 0x02
+#define BRIDGE_PCIE_CFG_BASE 0x03
+#define BRIDGE_PCIE_CFG_LIMIT 0x04
+#define BRIDGE_BUSNUM_BAR0 0x05
+#define BRIDGE_BUSNUM_BAR1 0x06
+#define BRIDGE_BUSNUM_BAR2 0x07
+#define BRIDGE_BUSNUM_BAR3 0x08
+#define BRIDGE_BUSNUM_BAR4 0x09
+#define BRIDGE_BUSNUM_BAR5 0x0a
+#define BRIDGE_BUSNUM_BAR6 0x0b
+#define BRIDGE_FLASH_BAR0 0x0c
+#define BRIDGE_FLASH_BAR1 0x0d
+#define BRIDGE_FLASH_BAR2 0x0e
+#define BRIDGE_FLASH_BAR3 0x0f
+#define BRIDGE_FLASH_LIMIT0 0x10
+#define BRIDGE_FLASH_LIMIT1 0x11
+#define BRIDGE_FLASH_LIMIT2 0x12
+#define BRIDGE_FLASH_LIMIT3 0x13
+
+#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
+#define BRIDGE_DRAM_BAR0 0x14
+#define BRIDGE_DRAM_BAR1 0x15
+#define BRIDGE_DRAM_BAR2 0x16
+#define BRIDGE_DRAM_BAR3 0x17
+#define BRIDGE_DRAM_BAR4 0x18
+#define BRIDGE_DRAM_BAR5 0x19
+#define BRIDGE_DRAM_BAR6 0x1a
+#define BRIDGE_DRAM_BAR7 0x1b
+
+#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0 0x1c
+#define BRIDGE_DRAM_LIMIT1 0x1d
+#define BRIDGE_DRAM_LIMIT2 0x1e
+#define BRIDGE_DRAM_LIMIT3 0x1f
+#define BRIDGE_DRAM_LIMIT4 0x20
+#define BRIDGE_DRAM_LIMIT5 0x21
+#define BRIDGE_DRAM_LIMIT6 0x22
+#define BRIDGE_DRAM_LIMIT7 0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
+#define BRIDGE_PCIEMEM_BASE0 0x34
+#define BRIDGE_PCIEMEM_BASE1 0x35
+#define BRIDGE_PCIEMEM_BASE2 0x36
+#define BRIDGE_PCIEMEM_BASE3 0x37
+#define BRIDGE_PCIEMEM_LIMIT0 0x38
+#define BRIDGE_PCIEMEM_LIMIT1 0x39
+#define BRIDGE_PCIEMEM_LIMIT2 0x3a
+#define BRIDGE_PCIEMEM_LIMIT3 0x3b
+#define BRIDGE_PCIEIO_BASE0 0x3c
+#define BRIDGE_PCIEIO_BASE1 0x3d
+#define BRIDGE_PCIEIO_BASE2 0x3e
+#define BRIDGE_PCIEIO_BASE3 0x3f
+#define BRIDGE_PCIEIO_LIMIT0 0x40
+#define BRIDGE_PCIEIO_LIMIT1 0x41
+#define BRIDGE_PCIEIO_LIMIT2 0x42
+#define BRIDGE_PCIEIO_LIMIT3 0x43
+#define BRIDGE_PCIEMEM_BASE4 0x44
+#define BRIDGE_PCIEMEM_BASE5 0x45
+#define BRIDGE_PCIEMEM_BASE6 0x46
+#define BRIDGE_PCIEMEM_LIMIT4 0x47
+#define BRIDGE_PCIEMEM_LIMIT5 0x48
+#define BRIDGE_PCIEMEM_LIMIT6 0x49
+#define BRIDGE_PCIEIO_BASE4 0x4a
+#define BRIDGE_PCIEIO_BASE5 0x4b
+#define BRIDGE_PCIEIO_BASE6 0x4c
+#define BRIDGE_PCIEIO_LIMIT4 0x4d
+#define BRIDGE_PCIEIO_LIMIT5 0x4e
+#define BRIDGE_PCIEIO_LIMIT6 0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
+#define BRIDGE_EVNTCTR1_LOW 0x51
+#define BRIDGE_EVNTCTR1_HI 0x52
+#define BRIDGE_EVNT_CNT_CTL2 0x53
+#define BRIDGE_EVNTCTR2_LOW 0x54
+#define BRIDGE_EVNTCTR2_HI 0x55
+#define BRIDGE_TRACEBUF_MATCH0 0x56
+#define BRIDGE_TRACEBUF_MATCH1 0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
+#define BRIDGE_TRACEBUF_MATCH_HI 0x59
+#define BRIDGE_TRACEBUF_CTRL 0x5a
+#define BRIDGE_TRACEBUF_INIT 0x5b
+#define BRIDGE_TRACEBUF_ACCESS 0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3 0x60
+#define BRIDGE_TRACEBUF_STATUS 0x61
+#define BRIDGE_ADDRESS_ERROR0 0x62
+#define BRIDGE_ADDRESS_ERROR1 0x63
+#define BRIDGE_ADDRESS_ERROR2 0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
+#define BRIDGE_LINE_FLUSH0 0x68
+#define BRIDGE_LINE_FLUSH1 0x69
+#define BRIDGE_NODE_ID 0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
+#define BRIDGE_PCIE0_WEIGHT 0x2c0
+#define BRIDGE_PCIE1_WEIGHT 0x2c1
+#define BRIDGE_PCIE2_WEIGHT 0x2c2
+#define BRIDGE_PCIE3_WEIGHT 0x2c3
+#define BRIDGE_USB_WEIGHT 0x2c4
+#define BRIDGE_NET_WEIGHT 0x2c5
+#define BRIDGE_POE_WEIGHT 0x2c6
+#define BRIDGE_CMS_WEIGHT 0x2c7
+#define BRIDGE_DMAENG_WEIGHT 0x2c8
+#define BRIDGE_SEC_WEIGHT 0x2c9
+#define BRIDGE_COMP_WEIGHT 0x2ca
+#define BRIDGE_GIO_WEIGHT 0x2cb
+#define BRIDGE_FLASH_WEIGHT 0x2cc
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
#define nlm_get_bridge_pcibase(node) \
- nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+ nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
#define nlm_get_bridge_regbase(node) \
- (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
+ (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
#endif
#endif
Modified: head/sys/mips/nlm/hal/cop2.h
==============================================================================
--- head/sys/mips/nlm/hal/cop2.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/cop2.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,29 +30,29 @@
*/
#ifndef __NLM_HAL_COP2_H__
-#define __NLM_HAL_COP2_H__
+#define __NLM_HAL_COP2_H__
-#define COP2_TX_BUF 0
-#define COP2_RX_BUF 1
-#define COP2_TXMSGSTATUS 2
-#define COP2_RXMSGSTATUS 3
-#define COP2_MSGSTATUS1 4
-#define COP2_MSGCONFIG 5
-#define COP2_MSGCONFIG1 6
-
-#define CROSSTHR_POPQ_EN 0x01
-#define VC0_POPQ_EN 0x02
-#define VC1_POPQ_EN 0x04
-#define VC2_POPQ_EN 0x08
-#define VC3_POPQ_EN 0x10
-#define ALL_VC_POPQ_EN 0x1E
-#define ALL_VC_CT_POPQ_EN 0x1F
+#define COP2_TX_BUF 0
+#define COP2_RX_BUF 1
+#define COP2_TXMSGSTATUS 2
+#define COP2_RXMSGSTATUS 3
+#define COP2_MSGSTATUS1 4
+#define COP2_MSGCONFIG 5
+#define COP2_MSGCONFIG1 6
+
+#define CROSSTHR_POPQ_EN 0x01
+#define VC0_POPQ_EN 0x02
+#define VC1_POPQ_EN 0x04
+#define VC2_POPQ_EN 0x08
+#define VC3_POPQ_EN 0x10
+#define ALL_VC_POPQ_EN 0x1E
+#define ALL_VC_CT_POPQ_EN 0x1F
struct nlm_fmn_msg {
uint64_t msg[4];
};
-#define NLM_DEFINE_COP2_ACCESSORS32(name, reg, sel) \
+#define NLM_DEFINE_COP2_ACCESSORS32(name, reg, sel) \
static inline uint32_t nlm_read_c2_##name(void) \
{ \
uint32_t __rv; \
@@ -79,7 +79,7 @@ static inline void nlm_write_c2_##name(u
} struct __hack
#if (__mips == 64)
-#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
+#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
static inline uint64_t nlm_read_c2_##name(void) \
{ \
uint64_t __rv; \
@@ -107,7 +107,7 @@ static inline void nlm_write_c2_##name(u
#else
-#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
+#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
static inline uint64_t nlm_read_c2_##name(void) \
{ \
uint32_t __high, __low; \
Modified: head/sys/mips/nlm/hal/cpucontrol.h
==============================================================================
--- head/sys/mips/nlm/hal/cpucontrol.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/cpucontrol.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,52 +30,52 @@
*/
#ifndef __NLM_HAL_CPUCONTROL_H__
-#define __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
-#define CPU_BLOCKID_IFU 0
-#define CPU_BLOCKID_ICU 1
-#define CPU_BLOCKID_IEU 2
-#define CPU_BLOCKID_LSU 3
-#define CPU_BLOCKID_MMU 4
-#define CPU_BLOCKID_PRF 5
-#define CPU_BLOCKID_SCH 7
-#define CPU_BLOCKID_SCU 8
-#define CPU_BLOCKID_FPU 9
-#define CPU_BLOCKID_MAP 10
-
-#define LSU_DEFEATURE 0x304
-#define LSU_CERRLOG_REGID 0x09
-#define SCHED_DEFEATURE 0x700
+#define CPU_BLOCKID_IFU 0
+#define CPU_BLOCKID_ICU 1
+#define CPU_BLOCKID_IEU 2
+#define CPU_BLOCKID_LSU 3
+#define CPU_BLOCKID_MMU 4
+#define CPU_BLOCKID_PRF 5
+#define CPU_BLOCKID_SCH 7
+#define CPU_BLOCKID_SCU 8
+#define CPU_BLOCKID_FPU 9
+#define CPU_BLOCKID_MAP 10
+
+#define LSU_DEFEATURE 0x304
+#define LSU_CERRLOG_REGID 0x09
+#define SCHED_DEFEATURE 0x700
/* Offsets of interest from the 'MAP' Block */
-#define MAP_THREADMODE 0x00
-#define MAP_EXT_EBASE_ENABLE 0x04
-#define MAP_CCDI_CONFIG 0x08
-#define MAP_THRD0_CCDI_STATUS 0x0c
-#define MAP_THRD1_CCDI_STATUS 0x10
-#define MAP_THRD2_CCDI_STATUS 0x14
-#define MAP_THRD3_CCDI_STATUS 0x18
-#define MAP_THRD0_DEBUG_MODE 0x1c
-#define MAP_THRD1_DEBUG_MODE 0x20
-#define MAP_THRD2_DEBUG_MODE 0x24
-#define MAP_THRD3_DEBUG_MODE 0x28
-#define MAP_MISC_STATE 0x60
-#define MAP_DEBUG_READ_CTL 0x64
-#define MAP_DEBUG_READ_REG0 0x68
-#define MAP_DEBUG_READ_REG1 0x6c
-
-#define MMU_SETUP 0x400
-#define MMU_LFSRSEED 0x401
-#define MMU_HPW_NUM_PAGE_LVL 0x410
-#define MMU_PGWKR_PGDBASE 0x411
-#define MMU_PGWKR_PGDSHFT 0x412
-#define MMU_PGWKR_PGDMASK 0x413
-#define MMU_PGWKR_PUDSHFT 0x414
-#define MMU_PGWKR_PUDMASK 0x415
-#define MMU_PGWKR_PMDSHFT 0x416
-#define MMU_PGWKR_PMDMASK 0x417
-#define MMU_PGWKR_PTESHFT 0x418
-#define MMU_PGWKR_PTEMASK 0x419
+#define MAP_THREADMODE 0x00
+#define MAP_EXT_EBASE_ENABLE 0x04
+#define MAP_CCDI_CONFIG 0x08
+#define MAP_THRD0_CCDI_STATUS 0x0c
+#define MAP_THRD1_CCDI_STATUS 0x10
+#define MAP_THRD2_CCDI_STATUS 0x14
+#define MAP_THRD3_CCDI_STATUS 0x18
+#define MAP_THRD0_DEBUG_MODE 0x1c
+#define MAP_THRD1_DEBUG_MODE 0x20
+#define MAP_THRD2_DEBUG_MODE 0x24
+#define MAP_THRD3_DEBUG_MODE 0x28
+#define MAP_MISC_STATE 0x60
+#define MAP_DEBUG_READ_CTL 0x64
+#define MAP_DEBUG_READ_REG0 0x68
+#define MAP_DEBUG_READ_REG1 0x6c
+
+#define MMU_SETUP 0x400
+#define MMU_LFSRSEED 0x401
+#define MMU_HPW_NUM_PAGE_LVL 0x410
+#define MMU_PGWKR_PGDBASE 0x411
+#define MMU_PGWKR_PGDSHFT 0x412
+#define MMU_PGWKR_PGDMASK 0x413
+#define MMU_PGWKR_PUDSHFT 0x414
+#define MMU_PGWKR_PUDMASK 0x415
+#define MMU_PGWKR_PMDSHFT 0x416
+#define MMU_PGWKR_PMDMASK 0x417
+#define MMU_PGWKR_PTESHFT 0x418
+#define MMU_PGWKR_PTEMASK 0x419
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
Modified: head/sys/mips/nlm/hal/haldefs.h
==============================================================================
--- head/sys/mips/nlm/hal/haldefs.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/haldefs.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,7 +30,7 @@
*/
#ifndef __NLM_HAL_MMIO_H__
-#define __NLM_HAL_MMIO_H__
+#define __NLM_HAL_MMIO_H__
/*
* This file contains platform specific memory mapped IO implementation
Modified: head/sys/mips/nlm/hal/iomap.h
==============================================================================
--- head/sys/mips/nlm/hal/iomap.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/iomap.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -32,91 +32,91 @@
#ifndef __NLM_HAL_IOMAP_H__
#define __NLM_HAL_IOMAP_H__
-#define XLP_DEFAULT_IO_BASE 0x18000000
-#define NMI_BASE 0xbfc00000
+#define XLP_DEFAULT_IO_BASE 0x18000000
+#define NMI_BASE 0xbfc00000
#define XLP_IO_CLK 133333333
-#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
-#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
-#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
-#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
-#define XLP_IO_PCI_HDRSZ 0x100
-#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
-#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
+#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
+#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
+#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
+#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
+#define XLP_IO_PCI_HDRSZ 0x100
+#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
+#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
-#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
+#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
/* coherent inter chip */
-#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
-#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
-#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
-#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
-
-#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
-#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
-#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
-#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
-#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
-
-#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
-#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
-#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
-#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
-#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
-#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
-#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
-
-#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
-#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
-
-#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
-
-#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
-#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
-#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
-
-#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
-#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
-#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
-#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
-#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
-#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
-#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
+#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
+#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
+#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
+#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
+
+#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
+#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
+#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
+#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
+#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
+
+#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
+#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
+#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
+#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
+#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
+#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
+#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
+
+#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
+#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
+
+#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
+
+#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
+#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
+#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
+
+#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
+#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
+#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
+#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + (i))
+#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
+#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
+#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
/* system management */
-#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
-#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
+#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
+#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
-#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
-#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
-#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
+#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
+#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
+#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
/* SD flash */
-#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot) \
- ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot) \
+ ((XLP_IO_SD_OFFSET(node)) + (slot * 0x100) + XLP_IO_PCI_HDRSZ)
/* PCI config header register id's */
-#define XLP_PCI_CFGREG0 0x00
-#define XLP_PCI_CFGREG1 0x01
-#define XLP_PCI_CFGREG2 0x02
-#define XLP_PCI_CFGREG3 0x03
-#define XLP_PCI_CFGREG4 0x04
-#define XLP_PCI_CFGREG5 0x05
-#define XLP_PCI_DEVINFO_REG0 0x30
-#define XLP_PCI_DEVINFO_REG1 0x31
-#define XLP_PCI_DEVINFO_REG2 0x32
-#define XLP_PCI_DEVINFO_REG3 0x33
-#define XLP_PCI_DEVINFO_REG4 0x34
-#define XLP_PCI_DEVINFO_REG5 0x35
-#define XLP_PCI_DEVINFO_REG6 0x36
-#define XLP_PCI_DEVINFO_REG7 0x37
-#define XLP_PCI_DEVSCRATCH_REG0 0x38
-#define XLP_PCI_DEVSCRATCH_REG1 0x39
-#define XLP_PCI_DEVSCRATCH_REG2 0x3a
-#define XLP_PCI_DEVSCRATCH_REG3 0x3b
-#define XLP_PCI_MSGSTN_REG 0x3c
-#define XLP_PCI_IRTINFO_REG 0x3d
-#define XLP_PCI_UCODEINFO_REG 0x3e
-#define XLP_PCI_SBB_WT_REG 0x3f
+#define XLP_PCI_CFGREG0 0x00
+#define XLP_PCI_CFGREG1 0x01
+#define XLP_PCI_CFGREG2 0x02
+#define XLP_PCI_CFGREG3 0x03
+#define XLP_PCI_CFGREG4 0x04
+#define XLP_PCI_CFGREG5 0x05
+#define XLP_PCI_DEVINFO_REG0 0x30
+#define XLP_PCI_DEVINFO_REG1 0x31
+#define XLP_PCI_DEVINFO_REG2 0x32
+#define XLP_PCI_DEVINFO_REG3 0x33
+#define XLP_PCI_DEVINFO_REG4 0x34
+#define XLP_PCI_DEVINFO_REG5 0x35
+#define XLP_PCI_DEVINFO_REG6 0x36
+#define XLP_PCI_DEVINFO_REG7 0x37
+#define XLP_PCI_DEVSCRATCH_REG0 0x38
+#define XLP_PCI_DEVSCRATCH_REG1 0x39
+#define XLP_PCI_DEVSCRATCH_REG2 0x3a
+#define XLP_PCI_DEVSCRATCH_REG3 0x3b
+#define XLP_PCI_MSGSTN_REG 0x3c
+#define XLP_PCI_IRTINFO_REG 0x3d
+#define XLP_PCI_UCODEINFO_REG 0x3e
+#define XLP_PCI_SBB_WT_REG 0x3f
/* PCI IDs for SoC device */
#define PCI_VENDOR_NETLOGIC 0x184e
@@ -142,8 +142,8 @@
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
-#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
extern uint64_t xlp_sys_base;
extern uint64_t xlp_pic_base;
Modified: head/sys/mips/nlm/hal/mips-extns.h
==============================================================================
--- head/sys/mips/nlm/hal/mips-extns.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/mips-extns.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,7 +30,7 @@
*/
#ifndef __NLM_MIPS_EXTNS_H__
-#define __NLM_MIPS_EXTNS_H__
+#define __NLM_MIPS_EXTNS_H__
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val)
@@ -115,7 +115,7 @@ nlm_ldaddwu(unsigned int value, unsigned
/*
* 32 bit read write for c0
*/
-#define read_c0_register32(reg, sel) \
+#define read_c0_register32(reg, sel) \
({ \
uint32_t __rv; \
__asm__ __volatile__( \
@@ -127,7 +127,7 @@ nlm_ldaddwu(unsigned int value, unsigned
__rv; \
})
-#define write_c0_register32(reg, sel, value) \
+#define write_c0_register32(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips32\n\t" \
@@ -139,7 +139,7 @@ nlm_ldaddwu(unsigned int value, unsigned
/*
* On 64 bit compilation, the operations are simple
*/
-#define read_c0_register64(reg, sel) \
+#define read_c0_register64(reg, sel) \
({ \
uint64_t __rv; \
__asm__ __volatile__( \
@@ -151,7 +151,7 @@ nlm_ldaddwu(unsigned int value, unsigned
__rv; \
})
-#define write_c0_register64(reg, sel, value) \
+#define write_c0_register64(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips64\n\t" \
@@ -163,7 +163,7 @@ nlm_ldaddwu(unsigned int value, unsigned
/*
* 32 bit compilation, 64 bit values has to split
*/
-#define read_c0_register64(reg, sel) \
+#define read_c0_register64(reg, sel) \
({ \
uint32_t __high, __low; \
__asm__ __volatile__( \
@@ -179,7 +179,7 @@ nlm_ldaddwu(unsigned int value, unsigned
((uint64_t)__high << 32) | __low; \
})
-#define write_c0_register64(reg, sel, value) \
+#define write_c0_register64(reg, sel, value) \
do { \
uint32_t __high = value >> 32; \
uint32_t __low = value & 0xffffffff; \
@@ -267,8 +267,8 @@ nlm_coreid(void)
}
#endif
-#define XLP_MAX_NODES 4
-#define XLP_MAX_CORES 8
-#define XLP_MAX_THREADS 4
+#define XLP_MAX_NODES 4
+#define XLP_MAX_CORES 8
+#define XLP_MAX_THREADS 4
#endif
Modified: head/sys/mips/nlm/hal/mmu.h
==============================================================================
--- head/sys/mips/nlm/hal/mmu.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/mmu.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,7 +30,7 @@
*/
#ifndef __XLP_MMU_H__
-#define __XLP_MMU_H__
+#define __XLP_MMU_H__
#include <mips/nlm/hal/mips-extns.h>
Modified: head/sys/mips/nlm/hal/pcibus.h
==============================================================================
--- head/sys/mips/nlm/hal/pcibus.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/pcibus.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,60 +30,60 @@
*/
#ifndef __XLP_PCIBUS_H__
-#define __XLP_PCIBUS_H__
+#define __XLP_PCIBUS_H__
-#define MSI_MIPS_ADDR_BASE 0xfee00000
+#define MSI_MIPS_ADDR_BASE 0xfee00000
/* MSI support */
-#define MSI_MIPS_ADDR_DEST 0x000ff000
-#define MSI_MIPS_ADDR_RH 0x00000008
-#define MSI_MIPS_ADDR_RH_OFF 0x00000000
-#define MSI_MIPS_ADDR_RH_ON 0x00000008
-#define MSI_MIPS_ADDR_DM 0x00000004
-#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
-#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
+#define MSI_MIPS_ADDR_DEST 0x000ff000
+#define MSI_MIPS_ADDR_RH 0x00000008
+#define MSI_MIPS_ADDR_RH_OFF 0x00000000
+#define MSI_MIPS_ADDR_RH_ON 0x00000008
+#define MSI_MIPS_ADDR_DM 0x00000004
+#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
+#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
/* Fields in data for Intel MSI messages. */
-#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
-#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
-#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
-
-#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
-#define MSI_MIPS_DATA_DEASSERT 0x00000000
-#define MSI_MIPS_DATA_ASSERT 0x00004000
-
-#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
-#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
-#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
+#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
+#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
+#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
+
+#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
+#define MSI_MIPS_DATA_DEASSERT 0x00000000
+#define MSI_MIPS_DATA_ASSERT 0x00004000
+
+#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
+#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
+#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
-#define MSI_MIPS_DATA_INTVEC 0x000000ff
+#define MSI_MIPS_DATA_INTVEC 0x000000ff
/*
* Build Intel MSI message and data values from a source. AMD64 systems
* seem to be compatible, so we use the same function for both.
*/
-#define MIPS_MSI_ADDR(cpu) \
- (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
- MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
-
-#define MIPS_MSI_DATA(irq) \
- (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
- MSI_MIPS_DATA_ASSERT | (irq))
-
-#define PCIE_BRIDGE_CMD 0x1
-#define PCIE_BRIDGE_MSI_CAP 0x14
-#define PCIE_BRIDGE_MSI_ADDRL 0x15
-#define PCIE_BRIDGE_MSI_ADDRH 0x16
-#define PCIE_BRIDGE_MSI_DATA 0x17
+#define MIPS_MSI_ADDR(cpu) \
+ (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
+ MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
+
+#define MIPS_MSI_DATA(irq) \
+ (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
+ MSI_MIPS_DATA_ASSERT | (irq))
+
+#define PCIE_BRIDGE_CMD 0x1
+#define PCIE_BRIDGE_MSI_CAP 0x14
+#define PCIE_BRIDGE_MSI_ADDRL 0x15
+#define PCIE_BRIDGE_MSI_ADDRH 0x16
+#define PCIE_BRIDGE_MSI_DATA 0x17
/* XLP Global PCIE configuration space registers */
-#define PCIE_MSI_STATUS 0x25A
-#define PCIE_MSI_EN 0x25B
-#define PCIE_INT_EN0 0x261
+#define PCIE_MSI_STATUS 0x25A
+#define PCIE_MSI_EN 0x25B
+#define PCIE_INT_EN0 0x261
/* PCIE_MSI_EN */
-#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
+#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
/* PCIE_INT_EN0 */
-#define PCIE_MSI_INT_EN (1 << 9)
+#define PCIE_MSI_INT_EN (1 << 9)
#endif /* __XLP_PCIBUS_H__ */
Modified: head/sys/mips/nlm/hal/uart.h
==============================================================================
--- head/sys/mips/nlm/hal/uart.h Sat Nov 19 13:33:30 2011 (r227721)
+++ head/sys/mips/nlm/hal/uart.h Sat Nov 19 14:06:15 2011 (r227722)
@@ -30,69 +30,69 @@
*/
#ifndef __XLP_HAL_UART_H__
-#define __XLP_HAL_UART_H__
+#define __XLP_HAL_UART_H__
/* UART Specific registers */
-#define UART_RX_DATA 0x00
-#define UART_TX_DATA 0x00
+#define UART_RX_DATA 0x00
+#define UART_TX_DATA 0x00
-#define UART_INT_EN 0x01
-#define UART_INT_ID 0x02
-#define UART_FIFO_CTL 0x02
-#define UART_LINE_CTL 0x03
-#define UART_MODEM_CTL 0x04
-#define UART_LINE_STS 0x05
-#define UART_MODEM_STS 0x06
+#define UART_INT_EN 0x01
+#define UART_INT_ID 0x02
+#define UART_FIFO_CTL 0x02
+#define UART_LINE_CTL 0x03
+#define UART_MODEM_CTL 0x04
+#define UART_LINE_STS 0x05
+#define UART_MODEM_STS 0x06
-#define UART_DIVISOR0 0x00
-#define UART_DIVISOR1 0x01
+#define UART_DIVISOR0 0x00
+#define UART_DIVISOR1 0x01
-#define BASE_BAUD (XLP_IO_CLK/16)
-#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
+#define BASE_BAUD (XLP_IO_CLK/16)
+#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
/* LCR mask values */
-#define LCR_5BITS 0x00
-#define LCR_6BITS 0x01
-#define LCR_7BITS 0x02
-#define LCR_8BITS 0x03
-#define LCR_STOPB 0x04
-#define LCR_PENAB 0x08
-#define LCR_PODD 0x00
-#define LCR_PEVEN 0x10
-#define LCR_PONE 0x20
-#define LCR_PZERO 0x30
-#define LCR_SBREAK 0x40
-#define LCR_EFR_ENABLE 0xbf
-#define LCR_DLAB 0x80
+#define LCR_5BITS 0x00
+#define LCR_6BITS 0x01
+#define LCR_7BITS 0x02
+#define LCR_8BITS 0x03
+#define LCR_STOPB 0x04
+#define LCR_PENAB 0x08
+#define LCR_PODD 0x00
+#define LCR_PEVEN 0x10
+#define LCR_PONE 0x20
+#define LCR_PZERO 0x30
+#define LCR_SBREAK 0x40
+#define LCR_EFR_ENABLE 0xbf
+#define LCR_DLAB 0x80
/* MCR mask values */
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DRS 0x04
-#define MCR_IE 0x08
-#define MCR_LOOPBACK 0x10
+#define MCR_DTR 0x01
+#define MCR_RTS 0x02
+#define MCR_DRS 0x04
+#define MCR_IE 0x08
+#define MCR_LOOPBACK 0x10
/* FCR mask values */
-#define FCR_RCV_RST 0x02
-#define FCR_XMT_RST 0x04
-#define FCR_RX_LOW 0x00
-#define FCR_RX_MEDL 0x40
-#define FCR_RX_MEDH 0x80
-#define FCR_RX_HIGH 0xc0
+#define FCR_RCV_RST 0x02
+#define FCR_XMT_RST 0x04
+#define FCR_RX_LOW 0x00
+#define FCR_RX_MEDL 0x40
+#define FCR_RX_MEDH 0x80
+#define FCR_RX_HIGH 0xc0
/* IER mask values */
-#define IER_ERXRDY 0x1
-#define IER_ETXRDY 0x2
-#define IER_ERLS 0x4
-#define IER_EMSC 0x8
+#define IER_ERXRDY 0x1
+#define IER_ETXRDY 0x2
+#define IER_ERLS 0x4
+#define IER_EMSC 0x8
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
-#define nlm_get_uart_pcibase(node, inst) \
+#define nlm_get_uart_pcibase(node, inst) \
nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
-#define nlm_get_uart_regbase(node, inst) \
+#define nlm_get_uart_regbase(node, inst) \
(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
static inline void
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