svn commit: r213597 - stable/8/sys/dev/mii
Pyun YongHyeon
yongari at FreeBSD.org
Fri Oct 8 18:58:01 UTC 2010
Author: yongari
Date: Fri Oct 8 18:58:01 2010
New Revision: 213597
URL: http://svn.freebsd.org/changeset/base/213597
Log:
MFC r212306-212307,212342:
r212306:
Remove trailing CR at EOL.
r212307:
Consistently use tab characters instead of tab + space characters.
No functional changes.
r212342:
Correct definition of T2 mode bit of MRBE Message Page 5 Next Page
Control Register.
Modified:
stable/8/sys/dev/mii/brgphy.c
stable/8/sys/dev/mii/brgphyreg.h
Directory Properties:
stable/8/sys/ (props changed)
stable/8/sys/amd64/include/xen/ (props changed)
stable/8/sys/cddl/contrib/opensolaris/ (props changed)
stable/8/sys/contrib/dev/acpica/ (props changed)
stable/8/sys/contrib/pf/ (props changed)
stable/8/sys/dev/xen/xenpci/ (props changed)
Modified: stable/8/sys/dev/mii/brgphy.c
==============================================================================
--- stable/8/sys/dev/mii/brgphy.c Fri Oct 8 18:51:28 2010 (r213596)
+++ stable/8/sys/dev/mii/brgphy.c Fri Oct 8 18:58:01 2010 (r213597)
@@ -140,7 +140,7 @@ static const struct mii_phydesc brgphys[
MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
- MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
+ MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
MII_PHY_DESC(BROADCOM2, BCM5906),
MII_PHY_END
};
@@ -242,11 +242,12 @@ brgphy_attach(device_t dev)
bsc->serdes_flags |= BRGPHY_5708S;
sc->mii_flags |= MIIF_HAVEFIBER;
break;
- case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
- bsc->serdes_flags |= BRGPHY_5709S;
- sc->mii_flags |= MIIF_HAVEFIBER;
- break;
- } break;
+ case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
+ bsc->serdes_flags |= BRGPHY_5709S;
+ sc->mii_flags |= MIIF_HAVEFIBER;
+ break;
+ }
+ break;
default:
device_printf(dev, "Unrecognized OUI for PHY!\n");
}
@@ -637,7 +638,7 @@ brgphy_status(struct mii_softc *sc)
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
- /* Check for MRBE auto-negotiated speed results. */
+ /* Check for MRBE auto-negotiated speed results. */
switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
mii->mii_media_active |= IFM_10_FL; break;
@@ -649,39 +650,39 @@ brgphy_status(struct mii_softc *sc)
mii->mii_media_active |= IFM_2500_SX; break;
}
- /* Check for MRBE auto-negotiated duplex results. */
+ /* Check for MRBE auto-negotiated duplex results. */
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
- } else if (bsc->serdes_flags & BRGPHY_5709S) {
+ } else if (bsc->serdes_flags & BRGPHY_5709S) {
- /* Select GP Status Block of the AN MMD, get autoneg results. */
- PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
+ /* Select GP Status Block of the AN MMD, get autoneg results. */
+ PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
- /* Restore IEEE0 block (assumed in all brgphy(4) code). */
- PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
+ /* Restore IEEE0 block (assumed in all brgphy(4) code). */
+ PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
- /* Check for MRBE auto-negotiated speed results. */
- switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
- case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
- mii->mii_media_active |= IFM_10_FL; break;
- case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
- mii->mii_media_active |= IFM_100_FX; break;
- case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
- mii->mii_media_active |= IFM_1000_SX; break;
- case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
- mii->mii_media_active |= IFM_2500_SX; break;
+ /* Check for MRBE auto-negotiated speed results. */
+ switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
+ case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
+ mii->mii_media_active |= IFM_10_FL; break;
+ case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
+ mii->mii_media_active |= IFM_100_FX; break;
+ case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
+ mii->mii_media_active |= IFM_1000_SX; break;
+ case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
+ mii->mii_media_active |= IFM_2500_SX; break;
}
- /* Check for MRBE auto-negotiated duplex results. */
+ /* Check for MRBE auto-negotiated duplex results. */
if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
- }
+ }
}
@@ -1127,50 +1128,50 @@ brgphy_reset(struct mii_softc *sc)
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
- /* Select the SerDes Digital block of the AN MMD. */
- PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
+ /* Select the SerDes Digital block of the AN MMD. */
+ PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
- /* Select the Over 1G block of the AN MMD. */
+ /* Select the Over 1G block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
- /* Enable autoneg "Next Page" to advertise 2.5G support. */
- val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
+ /* Enable autoneg "Next Page" to advertise 2.5G support. */
+ val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
else
val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
- /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
+ /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
- /* Enable MRBE speed autoneg. */
- val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
+ /* Enable MRBE speed autoneg. */
+ val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
BRGPHY_MRBE_MSG_PG5_NP_T2;
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
- /* Select the Clause 73 User B0 block of the AN MMD. */
- PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
+ /* Select the Clause 73 User B0 block of the AN MMD. */
+ PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
- /* Enable MRBE speed autoneg. */
+ /* Enable MRBE speed autoneg. */
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
- /* Restore IEEE0 block (assumed in all brgphy(4) code). */
- PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
+ /* Restore IEEE0 block (assumed in all brgphy(4) code). */
+ PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
brgphy_fixup_disable_early_dac(sc);
-
+
brgphy_jumbo_settings(sc, ifp->if_mtu);
brgphy_ethernet_wirespeed(sc);
} else {
Modified: stable/8/sys/dev/mii/brgphyreg.h
==============================================================================
--- stable/8/sys/dev/mii/brgphyreg.h Fri Oct 8 18:51:28 2010 (r213596)
+++ stable/8/sys/dev/mii/brgphyreg.h Fri Oct 8 18:58:01 2010 (r213597)
@@ -39,21 +39,21 @@
* Broadcom BCM5400 registers
*/
-#define BRGPHY_MII_BMCR 0x00
-#define BRGPHY_BMCR_RESET 0x8000
-#define BRGPHY_BMCR_LOOP 0x4000
-#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
-#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
-#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
-#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
+#define BRGPHY_MII_BMCR 0x00
+#define BRGPHY_BMCR_RESET 0x8000
+#define BRGPHY_BMCR_LOOP 0x4000
+#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
+#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
+#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
+#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
-#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
-#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
-#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
-
-#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
-#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
-#define BRGPHY_S10 0 /* 10mbps */
+#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
+#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
+#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
+
+#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
+#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
+#define BRGPHY_S10 0 /* 10mbps */
#define BRGPHY_MII_BMSR 0x01
#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
@@ -262,153 +262,153 @@
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
-/*******************************************************/
-/* Begin: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/* SerDes autoneg is different from copper */
-#define BRGPHY_SERDES_ANAR 0x04
-#define BRGPHY_SERDES_ANAR_FDX 0x0020
-#define BRGPHY_SERDES_ANAR_HDX 0x0040
-#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
-
-#define BRGPHY_SERDES_ANLPAR 0x05
-#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
-#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
-#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
-
-/*******************************************************/
-/* End: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*
- * Shadow register 0x1C, bit 15 is write enable,
- * bits 14-10 select function (0x00 to 0x1F).
- */
-#define BRGPHY_MII_SHADOW_1C 0x1C
-#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
-#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
-
+/*******************************************************/
+/* Begin: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/* SerDes autoneg is different from copper */
+#define BRGPHY_SERDES_ANAR 0x04
+#define BRGPHY_SERDES_ANAR_FDX 0x0020
+#define BRGPHY_SERDES_ANAR_HDX 0x0040
+#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
+
+#define BRGPHY_SERDES_ANLPAR 0x05
+#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
+#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
+#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
+
+/*******************************************************/
+/* End: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*
+ * Shadow register 0x1C, bit 15 is write enable,
+ * bits 14-10 select function (0x00 to 0x1F).
+ */
+#define BRGPHY_MII_SHADOW_1C 0x1C
+#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
+#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
+
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
-#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
+#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
/* When set, Regs 0-0x0F are 1000X, else 1000T */
-#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
+#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
+
+#define BRGPHY_MII_TEST1 0x1E
+#define BRGPHY_TEST1_TRIM_EN 0x0010
+#define BRGPHY_TEST1_CRC_EN 0x8000
+
+#define BRGPHY_MII_TEST2 0x1F
+
+/*******************************************************/
+/* End: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
+/* Autoneg Next Page Transmit 1 Regiser */
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
+
+/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
+#define BRGPHY_5708S_BLOCK_ADDR 0x1f
+#define BRGPHY_5708S_DIG_PG0 0x0000
+#define BRGPHY_5708S_DIG3_PG2 0x0002
+#define BRGPHY_5708S_TX_MISC_PG5 0x0005
+
+/* 5708S SerDes "Digital" Registers (page 0) */
+#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
+#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
+#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
+
+#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
+#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
+#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
+
+
+#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
+#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
+
+/* 5708S SerDes "Digital 3" Registers (page 2) */
+#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
+#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
+
+/* 5708S SerDes "TX Misc" Registers (page 5) */
+#define BRGPHY_5708S_PG5_2500STATUS1 0x10
+#define BRGPHY_5708S_PG5_TXACTL1 0x15
+#define BRGPHY_5708S_PG5_TXACTL3 0x17
+
+/*******************************************************/
+/* End: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
-#define BRGPHY_MII_TEST1 0x1E
-#define BRGPHY_TEST1_TRIM_EN 0x0010
-#define BRGPHY_TEST1_CRC_EN 0x8000
-
-#define BRGPHY_MII_TEST2 0x1F
-
-/*******************************************************/
-/* End: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
-/* Autoneg Next Page Transmit 1 Regiser */
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
-
-/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
-#define BRGPHY_5708S_BLOCK_ADDR 0x1f
-#define BRGPHY_5708S_DIG_PG0 0x0000
-#define BRGPHY_5708S_DIG3_PG2 0x0002
-#define BRGPHY_5708S_TX_MISC_PG5 0x0005
-
-/* 5708S SerDes "Digital" Registers (page 0) */
-#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
-#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
-#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
-
-#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
-#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
-#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
-
-
-#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
-#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
-
-/* 5708S SerDes "Digital 3" Registers (page 2) */
-#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
-#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
-
-/* 5708S SerDes "TX Misc" Registers (page 5) */
-#define BRGPHY_5708S_PG5_2500STATUS1 0x10
-#define BRGPHY_5708S_PG5_TXACTL1 0x15
-#define BRGPHY_5708S_PG5_TXACTL3 0x17
-
-/*******************************************************/
-/* End: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
/*******************************************************/
/* Begin: PHY register values for the 5709S SerDes PHY */
/*******************************************************/
/* 5709S SerDes "General Purpose Status" Registers */
-#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120
-#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300
-#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00
-#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008
-#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004
-#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001
+#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120
+#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300
+#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00
+#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008
+#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004
+#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001
/* 5709S SerDes "SerDes Digital" Registers */
-#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300
-#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010
-#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010
-#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001
+#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300
+#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010
+#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010
+#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001
/* 5709S SerDes "Over 1G" Registers */
-#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320
-#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19
+#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320
+#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19
/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */
-#define BRGPHY_BLOCK_ADDR_MRBE 0x8350
-#define BRGPHY_MRBE_MSG_PG5_NP 0x10
-#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001
-#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0001
+#define BRGPHY_BLOCK_ADDR_MRBE 0x8350
+#define BRGPHY_MRBE_MSG_PG5_NP 0x10
+#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001
+#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002
/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
-#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370
-#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12
+#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370
+#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12
#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000
#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000
-#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000
+#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000
/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
-#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0
+#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0
/* 5709S SerDes "Combo IEEE 0" Registers */
-#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0
+#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0
-#define BRGPHY_ADDR_EXT 0x1E
-#define BRGPHY_BLOCK_ADDR 0x1F
+#define BRGPHY_ADDR_EXT 0x1E
+#define BRGPHY_BLOCK_ADDR 0x1F
-#define BRGPHY_ADDR_EXT_AN_MMD 0x3800
+#define BRGPHY_ADDR_EXT_AN_MMD 0x3800
/*******************************************************/
/* End: PHY register values for the 5709S SerDes PHY */
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