svn commit: r209026 - in head/sys/ia64: ia64 include
Marcel Moolenaar
xcllnt at mac.com
Fri Jun 11 19:09:16 UTC 2010
On Jun 11, 2010, at 11:52 AM, Pyun YongHyeon wrote:
> On Fri, Jun 11, 2010 at 11:49:14AM -0700, Marcel Moolenaar wrote:
>>
>> On Jun 11, 2010, at 11:08 AM, Pyun YongHyeon wrote:
>>
>>> On Fri, Jun 11, 2010 at 11:06:06AM -0700, Marcel Moolenaar wrote:
>>>>
>>>> On Jun 11, 2010, at 10:50 AM, Pyun YongHyeon wrote:
>>>>
>>>>>>>>
>>>>>>>> I'm not clear why you even need bounce buffers for RX. The chip supports 64bit addresses with no boundary or alignment restrictions.
>>>>>>>>
>>>>>>>
>>>>>>> Some controllers have 4G boundary bug so bge(4) restricts dma
>>>>>>> address space.
>>>>>>
>>>>>> That limitation should be reflected in the boundary attribute of the tag, not the lowaddr/highaddr attributes.
>>>>>>
>>>>>
>>>>> Yes, but that needed more code. And I don't have these buggy
>>>>> controllers so I chose more simple way that would work even though
>>>>> it may be inefficient.
>>>>
>>>> Do you happen to know if one or both of the hardware I have access to
>>>> is the "buggy" hardware?
>>>>
>>>
>>> Yes, both devices below can not handle 4GB boundary crossing in DMA
>>> state machine.
>>
>> Thanks. I'll keep that in mind. If I have a few cycles I'll patch the
>> kernel to allow 64-bit DMA addresses with a 4G boundary restriction
>> and run that through stress2.
>>
>
> I'll let you know when I have a patch to try on your box. I'm not sure
> when that could be done though.
Not to worry. I appreciate your support. Just let me know when you want
me to test something.
--
Marcel Moolenaar
xcllnt at mac.com
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