svn commit: r209026 - in head/sys/ia64: ia64 include
Pyun YongHyeon
pyunyh at gmail.com
Fri Jun 11 18:09:46 UTC 2010
On Fri, Jun 11, 2010 at 11:06:06AM -0700, Marcel Moolenaar wrote:
>
> On Jun 11, 2010, at 10:50 AM, Pyun YongHyeon wrote:
>
> >>>>
> >>>> I'm not clear why you even need bounce buffers for RX. The chip supports 64bit addresses with no boundary or alignment restrictions.
> >>>>
> >>>
> >>> Some controllers have 4G boundary bug so bge(4) restricts dma
> >>> address space.
> >>
> >> That limitation should be reflected in the boundary attribute of the tag, not the lowaddr/highaddr attributes.
> >>
> >
> > Yes, but that needed more code. And I don't have these buggy
> > controllers so I chose more simple way that would work even though
> > it may be inefficient.
>
> Do you happen to know if one or both of the hardware I have access to
> is the "buggy" hardware?
>
Yes, both devices below can not handle 4GB boundary crossing in DMA
state machine.
> bge0 at pci0:32:2:0: class=0x020000 card=0x12a4103c chip=0x164514e4 rev=0x15 hdr=0x00
> vendor = 'Broadcom Corporation'
> device = 'broadtcomBCM5701 Gigabit Ethernet (BCM5701)'
> class = network
> subclass = ethernet
> bar [10] = type Memory, range 64, base 0x90800000, size 65536, enabled
> cap 07[40] = PCI-X 64-bit supports 133MHz, 512 burst read, 1 split transaction
> cap 01[48] = powerspec 2 supports D0 D3 current D0
> cap 03[50] = VPD
> cap 05[58] = MSI supports 8 messages, 64 bit
>
> bge0 at pci0:1:2:0: class=0x020000 card=0x1311103c chip=0x164814e4 rev=0x10 hdr=0x00
> vendor = 'Broadcom Corporation'
> device = 'NetXtreme Dual Gigabit Adapter (BCM5704)'
> class = network
> subclass = ethernet
> bar [10] = type Memory, range 64, base 0xa0450000, size 65536, enabled
> cap 07[40] = PCI-X 64-bit supports 133MHz, 2048 burst read, 1 split transaction
> cap 01[48] = powerspec 2 supports D0 D3 current D0
> cap 03[50] = VPD
> cap 05[58] = MSI supports 8 messages, 64 bit
>
> --
> Marcel Moolenaar
> xcllnt at mac.com
>
>
>
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