svn commit: r209026 - in head/sys/ia64: ia64 include

[Scott Long]

On Jun 11, 2010, at 11:44 AM, Marcel Moolenaar wrote:
> 
> On Jun 11, 2010, at 10:37 AM, Scott Long wrote:
>> 
>> I'm not clear why you even need bounce buffers for RX.  The chip supports 64bit addresses with no boundary or alignment restrictions.
> 
> As per:
>        /*
>         * All controllers that are not 5755 or higher have 4GB
>         * boundary DMA bug.
>         * Whenever an address crosses a multiple of the 4GB boundary
>         * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
>         * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
>         * state machine will lockup and cause the device to hang.
>         */
>        if (BGE_IS_5755_PLUS(sc) == 0)
>                sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
> 
> and:
>        lowaddr = BUS_SPACE_MAXADDR;
>        if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
>                lowaddr = BGE_DMA_MAXADDR;
>        if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
>                lowaddr = BUS_SPACE_MAXADDR_32BIT;
>        /*
>         * Allocate the parent bus DMA tag appropriate for PCI.
>         */
>        error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
>            1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
>            NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
>            0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
> 
> 

Noted in previous email.  If this restriction is put in the boundary attribute, then you'll only bounce the very rare case of an mbuf straddling a 4G boundary.

Scott