svn commit: r204365 - head/sys/dev/msk

[Pyun YongHyeon]

Author: yongari
Date: Fri Feb 26 19:18:29 2010
New Revision: 204365
URL: http://svn.freebsd.org/changeset/base/204365

Log:
  Don't hardcod register offset to set PCIe max read request size.
  The register offset is not valid on 88E8072 controller. Also don't
  blindly increase max read request size to 4096, instead, use 2048
  which seems to be more sane value and only change the value if the
  hardware default size(512) was used on that register.
  For PCIX controllers, use system defined constant rather than using
  magic value.
  While I'm here stop showing negotiated link width.

Modified:
  head/sys/dev/msk/if_msk.c
  head/sys/dev/msk/if_mskreg.h

Modified: head/sys/dev/msk/if_msk.c
==============================================================================
--- head/sys/dev/msk/if_msk.c	Fri Feb 26 18:46:16 2010	(r204364)
+++ head/sys/dev/msk/if_msk.c	Fri Feb 26 19:18:29 2010	(r204365)
@@ -1356,35 +1356,22 @@ mskc_reset(struct msk_softc *sc)
          * On dual port PCI-X card, there is an problem where status
          * can be received out of order due to split transactions.
          */
-	if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) {
-		int pcix;
+	if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
 		uint16_t pcix_cmd;
 
-		if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) {
-			pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2);
-			/* Clear Max Outstanding Split Transactions. */
-			pcix_cmd &= ~0x70;
-			CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
-			pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2);
-			CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
-		}
+		pcix_cmd = pci_read_config(sc->msk_dev,
+		    sc->msk_pcixcap + PCIXR_COMMAND, 2);
+		/* Clear Max Outstanding Split Transactions. */
+		pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
+		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+		pci_write_config(sc->msk_dev,
+		    sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
+		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
         }
-	if (sc->msk_bustype == MSK_PEX_BUS) {
-		uint16_t v, width;
-
-		v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2);
-		/* Change Max. Read Request Size to 4096 bytes. */
-		v &= ~PEX_DC_MAX_RRS_MSK;
-		v |= PEX_DC_MAX_RD_RQ_SIZE(5);
-		pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2);
-		width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2);
-		width = (width & PEX_LS_LINK_WI_MSK) >> 4;
-		v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2);
-		v = (v & PEX_LS_LINK_WI_MSK) >> 4;
-		if (v != width)
-			device_printf(sc->msk_dev,
-			    "negotiated width of link(x%d) != "
-			    "max. width of link(x%d)\n", width, v); 
+	if (sc->msk_expcap != 0) {
+		/* Change Max. Read Request Size to 2048 bytes. */
+		if (pci_get_max_read_req(sc->msk_dev) == 512)
+			pci_set_max_read_req(sc->msk_dev, 2048);
 	}
 
 	/* Clear status list. */
@@ -1694,11 +1681,13 @@ mskc_attach(device_t dev)
 	}
 
 	/* Check bus type. */
-	if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, &reg) == 0)
+	if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, &reg) == 0) {
 		sc->msk_bustype = MSK_PEX_BUS;
-	else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &reg) == 0)
+		sc->msk_expcap = reg;
+	} else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &reg) == 0) {
 		sc->msk_bustype = MSK_PCIX_BUS;
-	else
+		sc->msk_pcixcap = reg;
+	} else
 		sc->msk_bustype = MSK_PCI_BUS;
 
 	switch (sc->msk_hw_id) {

Modified: head/sys/dev/msk/if_mskreg.h
==============================================================================
--- head/sys/dev/msk/if_mskreg.h	Fri Feb 26 18:46:16 2010	(r204364)
+++ head/sys/dev/msk/if_mskreg.h	Fri Feb 26 19:18:29 2010	(r204365)
@@ -2476,6 +2476,8 @@ struct msk_softc {
 	uint8_t			msk_hw_rev;
 	uint8_t			msk_bustype;
 	uint8_t			msk_num_port;
+	int			msk_expcap;
+	int			msk_pcixcap;
 	int			msk_ramsize;	/* amount of SRAM on NIC */
 	uint32_t		msk_pmd;	/* physical media type */
 	uint32_t		msk_intrmask;