svn commit: r199833 - stable/8/sys/dev/ata/chipsets

[Alexander Motin]

Author: mav
Date: Thu Nov 26 14:56:58 2009
New Revision: 199833
URL: http://svn.freebsd.org/changeset/base/199833

Log:
  MFC r199645, r199646:
  Fix Intel PATA UDMA timings setting, affecting write performance.
  Binary divider value 10 specified in datasheet is not a hex 0x10.
  UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
  UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
  Release over-agressive WDMA0 mode timings as close to spec as chip can.

Modified:
  stable/8/sys/dev/ata/chipsets/ata-intel.c
Directory Properties:
  stable/8/sys/   (props changed)
  stable/8/sys/amd64/include/xen/   (props changed)
  stable/8/sys/cddl/contrib/opensolaris/   (props changed)
  stable/8/sys/contrib/dev/acpica/   (props changed)
  stable/8/sys/contrib/pf/   (props changed)
  stable/8/sys/dev/xen/xenpci/   (props changed)

Modified: stable/8/sys/dev/ata/chipsets/ata-intel.c
==============================================================================
--- stable/8/sys/dev/ata/chipsets/ata-intel.c	Thu Nov 26 14:52:14 2009	(r199832)
+++ stable/8/sys/dev/ata/chipsets/ata-intel.c	Thu Nov 26 14:56:58 2009	(r199833)
@@ -301,7 +301,7 @@ ata_intel_new_setmode(device_t dev, int 
     u_int32_t mask40 = 0, new40 = 0;
     u_int8_t mask44 = 0, new44 = 0;
     int error;
-    u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
+    u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23,
 			   0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
 
     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
@@ -319,7 +319,7 @@ ata_intel_new_setmode(device_t dev, int 
 		      ata_mode2str(mode), ctlr->chip->text);
     if (!error) {
 	if (mode >= ATA_UDMA0) {
-	    u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
+	    u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
 
 	    pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
 	    pci_write_config(gparent, 0x4a,
@@ -331,7 +331,7 @@ ata_intel_new_setmode(device_t dev, int 
 	    pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
 	}
 	reg54 |= 0x0400;
-	if (mode >= ATA_UDMA2)
+	if (mode >= ATA_UDMA3)
 	    reg54 |= (0x1 << devno);
 	else
 	    reg54 &= ~(0x1 << devno);