svn commit: r183984 - in stable/7/sys: . i386/i386 i386/include
John Baldwin
jhb at FreeBSD.org
Fri Oct 17 19:52:35 UTC 2008
Author: jhb
Date: Fri Oct 17 19:52:35 2008
New Revision: 183984
URL: http://svn.freebsd.org/changeset/base/183984
Log:
MFC: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB
large pages.
Approved by: re (kib)
Modified:
stable/7/sys/ (props changed)
stable/7/sys/i386/i386/identcpu.c
stable/7/sys/i386/include/specialreg.h
Modified: stable/7/sys/i386/i386/identcpu.c
==============================================================================
--- stable/7/sys/i386/i386/identcpu.c Fri Oct 17 18:19:36 2008 (r183983)
+++ stable/7/sys/i386/i386/identcpu.c Fri Oct 17 19:52:35 2008 (r183984)
@@ -720,7 +720,7 @@ printcpuinfo(void)
"\020"
"\001SSE3" /* SSE3 */
"\002<b1>"
- "\003RSVD2" /* "Reserved" bit 2 */
+ "\003DTES64" /* 64-bit Debug Trace */
"\004MON" /* MONITOR/MWAIT Instructions */
"\005DS_CPL" /* CPL Qualified Debug Store */
"\006VMX" /* Virtual Machine Extensions */
@@ -737,11 +737,11 @@ printcpuinfo(void)
"\021<b16>"
"\022<b17>"
"\023DCA" /* Direct Cache Access */
- "\024<b19>"
- "\025<b20>"
- "\026<b21>"
+ "\024SSE4.1"
+ "\025SSE4.2"
+ "\026x2APIC" /* xAPIC Extensions */
"\027<b22>"
- "\030<b23>"
+ "\030POPCNT"
"\031<b24>"
"\032<b25>"
"\033<b26>"
@@ -791,7 +791,7 @@ printcpuinfo(void)
"\030<s23>" /* Same */
"\031<s24>" /* Same */
"\032FFXSR" /* Fast FXSAVE/FXRSTOR */
- "\033<b26>" /* Undefined */
+ "\033Page1GB" /* 1-GB large page support */
"\034RDTSCP" /* RDTSCP */
"\035<b28>" /* Undefined */
"\036LM" /* 64 bit long mode */
Modified: stable/7/sys/i386/include/specialreg.h
==============================================================================
--- stable/7/sys/i386/include/specialreg.h Fri Oct 17 18:19:36 2008 (r183983)
+++ stable/7/sys/i386/include/specialreg.h Fri Oct 17 19:52:35 2008 (r183984)
@@ -110,6 +110,7 @@
#define CPUID_PBE 0x80000000
#define CPUID2_SSE3 0x00000001
+#define CPUID2_DTES64 0x00000004
#define CPUID2_MON 0x00000008
#define CPUID2_DS_CPL 0x00000010
#define CPUID2_VMX 0x00000020
@@ -122,6 +123,10 @@
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
#define CPUID2_DCA 0x00040000
+#define CPUID2_SSE41 0x00080000
+#define CPUID2_SSE42 0x00100000
+#define CPUID2_X2APIC 0x00200000
+#define CPUID2_POPCNT 0x00800000
/*
* Important bits in the AMD extended cpuid flags
@@ -131,6 +136,7 @@
#define AMDID_NX 0x00100000
#define AMDID_EXT_MMX 0x00400000
#define AMDID_FFXSR 0x01000000
+#define AMDID_PAGE1GB 0x04000000
#define AMDID_RDTSCP 0x08000000
#define AMDID_LM 0x20000000
#define AMDID_EXT_3DNOW 0x40000000
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