svn commit: r185162 - in head: . sys/amd64/include sys/arm/include sys/conf sys/dev/bce sys/dev/cxgb sys/dev/cxgb/sys sys/dev/cxgb/ulp/iw_cxgb sys/dev/mxge sys/dev/nxge sys/i386/include sys/i386/in...

[Scott Long]

A neat hack would be for the kernel linker to scan the text and do a
drop-in replacement of the opcode that is appropriate for the platform.
I can't see how a CPU_XXX definition would work because it's just a
compile time construct, one that can be included with any kernel
compile.

Scott


kmacy at FreeBSD.org wrote:
> This was a concern of mine - note that many driver writers assume they exist.
> 
> Thoughts on efficiently handling it via checking cpuid at runtime?
> Alternatively we could have it be conditional on  CPU_i786.
> 
> On 11/22/08, Kostik Belousov <kostikbel at gmail.com> wrote:
>> On Sat, Nov 22, 2008 at 05:55:56AM +0000, Kip Macy wrote:
>>> Author: kmacy
>>> Date: Sat Nov 22 05:55:56 2008
>>> New Revision: 185162
>>> URL: http://svn.freebsd.org/changeset/base/185162
>>>
>>> Log:
>>>   - bump __FreeBSD version to reflect added buf_ring, memory barriers,
>>>     and ifnet functions
>>>
>>>   - add memory barriers to <machine/atomic.h>
>>> Modified: head/sys/i386/include/atomic.h
>>> ==============================================================================
>>> --- head/sys/i386/include/atomic.h	Sat Nov 22 01:48:20 2008	(r185161)
>>> +++ head/sys/i386/include/atomic.h	Sat Nov 22 05:55:56 2008	(r185162)
>>> @@ -32,6 +32,21 @@
>>>  #error this file needs sys/cdefs.h as a prerequisite
>>>  #endif
>>>
>>> +
>>> +#if defined(I686_CPU)
>>> +#define mb()	__asm__ __volatile__ ("mfence;": : :"memory")
>>> +#define wmb()	__asm__ __volatile__ ("sfence;": : :"memory")
>>> +#define rmb()	__asm__ __volatile__ ("lfence;": : :"memory")
>>> +#else
>>> +/*
>>> + * do we need a serializing instruction?
>>> + */
>>> +#define mb()
>>> +#define wmb()
>>> +#define rmb()
>>> +#endif
>>> +
>>> +
>>>  /*
>>>   * Various simple operations on memory, each of which is atomic in the
>>>   * presence of interrupts and multiple processors.
>> AFAIR, sfence instruction was added with the Pentium III processor (SSE),
>> while lfence was introduced with the Pentium 4 (SSE2).
>>
>> I think that #ifdef I686_CPU handling of the fences is wrong. We need to
>> use a serialized instruction on CPUs that does not support corresponding
>> fence, if needed.
>>
> 
>