svn commit: r438668 - in head/devel/llvm40: . files
Brooks Davis
brooks at FreeBSD.org
Sun Apr 16 19:30:48 UTC 2017
Author: brooks
Date: Sun Apr 16 19:30:46 2017
New Revision: 438668
URL: https://svnweb.freebsd.org/changeset/ports/438668
Log:
Add a patch for upstream r300404:
Use correct registers for "A" inline asm constraint
Summary:
In PR32594, inline assembly using the 'A' constraint on x86_64 causes
llvm to crash with a "Cannot select" stack trace. This is because
`X86TargetLowering::getRegForInlineAsmConstraint` hardcodes that 'A'
means the EAX and EDX registers.
However, on x86_64 it means the RAX and RDX registers, and on 16-bit x86
(ia16?) it means the old AX and DX registers.
Add new register classes in `X86RegisterInfo.td` to support these cases,
and amend the logic in `getRegForInlineAsmConstraint` to cope with
different subtargets. Also add a test case, derived from PR32594.
Submitted by: dim
Added:
head/devel/llvm40/files/patch-svn-300404 (contents, props changed)
Modified:
head/devel/llvm40/Makefile
Modified: head/devel/llvm40/Makefile
==============================================================================
--- head/devel/llvm40/Makefile Sun Apr 16 18:31:54 2017 (r438667)
+++ head/devel/llvm40/Makefile Sun Apr 16 19:30:46 2017 (r438668)
@@ -2,7 +2,7 @@
PORTNAME= llvm
DISTVERSION= 4.0.0
-PORTREVISION= 2
+PORTREVISION= 3
CATEGORIES= devel lang
MASTER_SITES= http://llvm.org/${PRE_}releases/${LLVM_RELEASE}/${RCDIR}
PKGNAMESUFFIX= ${LLVM_SUFFIX}
@@ -464,6 +464,17 @@ check-commands:
test -e ${STAGEDIR}${LLVM_PREFIX}/bin/${command}
.endfor
+.if make(svn-patch-llvm)
+.if !defined(PATCH_REV)
+.error svn-patch-llvm requires that PATCH_REV be set
+.endif
+_PATCH_FILE=${FILESDIR}/patch-svn-${PATCH_REV}
+_LLVM_BASE=http://llvm.org/svn/llvm-project/llvm/trunk
+svn-patch-llvm:
+ svn log -c ${PATCH_REV} ${_LLVM_BASE} >> ${_PATCH_FILE}
+ svn diff -c ${PATCH_REV} ${_LLVM_BASE} >> ${_PATCH_FILE}
+.endif
+
.if make(svn-patch-clang)
.if !defined(PATCH_REV)
.error svn-patch-clang requires that PATCH_REV be set
@@ -475,6 +486,7 @@ svn-patch-clang:
svn diff -c ${PATCH_REV} ${_LLVM_BASE} | \
${SED} -E -e 's;^(---|\+\+\+) ;\1 tools/clang/;' >> ${_PATCH_FILE}
.endif
+
.if make(svn-patch-compiler-rt)
.if !defined(PATCH_REV)
.error svn-patch-compiler-rt requires that PATCH_REV be set
@@ -486,6 +498,7 @@ svn-patch-compiler-rt:
svn diff -c ${PATCH_REV} ${_LLVM_BASE} | \
${SED} -E -e 's;^(---|\+\+\+) ;\1 tools/compiler-rt/;' >> ${_PATCH_FILE}
.endif
+
.if make(svn-patch-lldb)
.if !defined(PATCH_REV)
.error svn-patch-lldb requires that PATCH_REV be set
Added: head/devel/llvm40/files/patch-svn-300404
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/llvm40/files/patch-svn-300404 Sun Apr 16 19:30:46 2017 (r438668)
@@ -0,0 +1,110 @@
+------------------------------------------------------------------------
+r300404 | dim | 2017-04-15 22:15:01 +0000 (Sat, 15 Apr 2017) | 22 lines
+
+Use correct registers for "A" inline asm constraint
+
+Summary:
+In PR32594, inline assembly using the 'A' constraint on x86_64 causes
+llvm to crash with a "Cannot select" stack trace. This is because
+`X86TargetLowering::getRegForInlineAsmConstraint` hardcodes that 'A'
+means the EAX and EDX registers.
+
+However, on x86_64 it means the RAX and RDX registers, and on 16-bit x86
+(ia16?) it means the old AX and DX registers.
+
+Add new register classes in `X86RegisterInfo.td` to support these cases,
+and amend the logic in `getRegForInlineAsmConstraint` to cope with
+different subtargets. Also add a test case, derived from PR32594.
+
+Reviewers: craig.topper, qcolombet, RKSimon, ab
+
+Reviewed By: ab
+
+Subscribers: ab, emaste, royger, llvm-commits
+
+Differential Revision: https://reviews.llvm.org/D31902
+------------------------------------------------------------------------
+Index: test/CodeGen/X86/inline-asm-A-constraint.ll
+===================================================================
+--- test/CodeGen/X86/inline-asm-A-constraint.ll (nonexistent)
++++ test/CodeGen/X86/inline-asm-A-constraint.ll (revision 300404)
+@@ -0,0 +1,35 @@
++; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
++
++target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
++target triple = "x86_64--"
++
++; Function Attrs: nounwind uwtable
++define { i64, i64 } @foo(i8* %ptr, i128* nocapture readonly %src, i128* nocapture readonly %dst) local_unnamed_addr #0 {
++entry:
++ %0 = load i128, i128* %dst, align 16, !tbaa !1
++ %shr = lshr i128 %0, 64
++ %conv = trunc i128 %shr to i64
++ %conv1 = trunc i128 %0 to i64
++ %1 = load i128, i128* %src, align 16, !tbaa !1
++ %2 = tail call i128 asm sideeffect "lock; cmpxchg16b $1", "=A,=*m,{cx},{bx},0,*m,~{dirflag},~{fpsr},~{flags}"(i8* %ptr, i64 %conv, i64 %conv1, i128 %1, i8* %ptr) #1, !srcloc !5
++ %retval.sroa.0.0.extract.trunc = trunc i128 %2 to i64
++ %retval.sroa.2.0.extract.shift = lshr i128 %2, 64
++ %retval.sroa.2.0.extract.trunc = trunc i128 %retval.sroa.2.0.extract.shift to i64
++ %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.extract.trunc, 0
++ %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.2.0.extract.trunc, 1
++ ret { i64, i64 } %.fca.1.insert
++}
++; CHECK: lock
++; CHECK-NEXT: cmpxchg16b
++
++attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
++attributes #1 = { nounwind }
++
++!llvm.ident = !{!0}
++
++!0 = !{!"clang version 5.0.0 (trunk 300088)"}
++!1 = !{!2, !2, i64 0}
++!2 = !{!"__int128", !3, i64 0}
++!3 = !{!"omnipotent char", !4, i64 0}
++!4 = !{!"Simple C/C++ TBAA"}
++!5 = !{i32 269}
+Index: lib/Target/X86/X86RegisterInfo.td
+===================================================================
+--- lib/Target/X86/X86RegisterInfo.td (revision 300403)
++++ lib/Target/X86/X86RegisterInfo.td (revision 300404)
+@@ -437,8 +437,10 @@
+ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
+ (add LOW32_ADDR_ACCESS, RBP)>;
+
+-// A class to support the 'A' assembler constraint: EAX then EDX.
++// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
++def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
+ def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
++def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
+
+ // Scalar SSE2 floating point registers.
+ def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
+Index: lib/Target/X86/X86ISelLowering.cpp
+===================================================================
+--- lib/Target/X86/X86ISelLowering.cpp (revision 300403)
++++ lib/Target/X86/X86ISelLowering.cpp (revision 300404)
+@@ -35917,10 +35917,20 @@
+ return Res;
+ }
+
+- // 'A' means EAX + EDX.
++ // 'A' means [ER]AX + [ER]DX.
+ if (Constraint == "A") {
+- Res.first = X86::EAX;
+- Res.second = &X86::GR32_ADRegClass;
++ if (Subtarget.is64Bit()) {
++ Res.first = X86::RAX;
++ Res.second = &X86::GR64_ADRegClass;
++ } else if (Subtarget.is32Bit()) {
++ Res.first = X86::EAX;
++ Res.second = &X86::GR32_ADRegClass;
++ } else if (Subtarget.is16Bit()) {
++ Res.first = X86::AX;
++ Res.second = &X86::GR16_ADRegClass;
++ } else {
++ llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
++ }
+ return Res;
+ }
+ return Res;
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