svn commit: r308558 - in head/comms: . usrp usrp/files
Diane Bruce
db at FreeBSD.org
Sun Dec 9 19:43:06 UTC 2012
Author: db
Date: Sun Dec 9 19:43:02 2012
New Revision: 308558
URL: http://svnweb.freebsd.org/changeset/ports/308558
Log:
UHD is the "Universal Software Radio Peripheral" (USRP) Hardware Driver. It
works on all major platforms (Linux, Windows, and Mac); and can be built with
GCC, Clang, and MSVC compilers.
The goal of UHD is to provide a host driver and API for current and
future Ettus Research products. Users will be able to use the UHD driver
standalone or with third-party applications such as:
GNU Radio
LabVIEW
Simulink
OpenBTS
Submitted by: adrian@
Reviewed by: db@
Added:
head/comms/usrp/
head/comms/usrp/Makefile (contents, props changed)
head/comms/usrp/distinfo (contents, props changed)
head/comms/usrp/files/
head/comms/usrp/files/patch-firmware_fx2_CMakeLists.txt (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_CMakeLists.txt (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_board_specific.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_fpga_load.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_fpga_rev2.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_gpif.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_usrp_main.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_b100_usrp_regs.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_delay.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_eeprom_init.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_fpga_load.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_fx2regs.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_fx2utils.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_i2c.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_i2c.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_isr.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_spi.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_spi.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_syncdelay.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_usb_common.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_usb_common.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_common_usb_descriptors.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_config_CMakeDetermineASM_SDCCCompiler.cmake (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_config_Toolchain-sdcc.cmake (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_board_specific.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_eeprom_io.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_eeprom_io.h (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_fpga_load.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_fpga_rev2.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_gpif.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_usrp_main.c (contents, props changed)
head/comms/usrp/files/patch-firmware_fx2_usrp1_usrp_regs.h (contents, props changed)
head/comms/usrp/files/patch-host_CMakeLists.txt (contents, props changed)
head/comms/usrp/files/patch-images_Makefile (contents, props changed)
head/comms/usrp/pkg-descr (contents, props changed)
head/comms/usrp/pkg-plist (contents, props changed)
Modified:
head/comms/Makefile
Modified: head/comms/Makefile
==============================================================================
--- head/comms/Makefile Sun Dec 9 19:40:44 2012 (r308557)
+++ head/comms/Makefile Sun Dec 9 19:43:02 2012 (r308558)
@@ -160,6 +160,7 @@
SUBDIR += umcs7840
SUBDIR += unixcw
SUBDIR += usbmuxd
+ SUBDIR += usrp
SUBDIR += uticom
SUBDIR += viewfax
SUBDIR += vrflash
Added: head/comms/usrp/Makefile
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/Makefile Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,118 @@
+# $FreeBSD$
+
+PORTNAME= usrp
+PORTVERSION= 3.4.3
+CATEGORIES= comms hamradio
+MASTER_SITES= ${MASTER_SITE_LOCAL}
+MASTER_SITE_SUBDIR= adrian
+DISTNAME= Ettus-USRP-3.4.3
+
+MAINTAINER= adrian at freebsd.org
+COMMENT= Ettus Research USRP driver framework
+
+LIB_DEPENDS= boost_python:${PORTSDIR}/devel/boost-python-libs
+BUILD_DEPENDS= ${LOCALBASE}/include/boost/tuple/tuple.hpp:${PORTSDIR}/devel/boost-libs \
+ cheetah-analyze:${PORTSDIR}/devel/py-cheetah \
+ rst2html:${PORTSDIR}/textproc/py-docutils \
+ orcc:${PORTSDIR}/devel/orc \
+ sdcc:${PORTSDIR}/lang/sdcc
+
+USE_DOS2UNIX= yes
+USE_CMAKE= yes
+USE_GMAKE= yes
+USE_LDCONFIG= yes
+CMAKE_OUTSOURCE= yes
+
+# for excruciating debug use this -db
+CMAKE_ARGS= --debug-output --trace
+DOCSDIR= share/doc/uhd
+WRKSRC= ${WRKDIR}/EttusResearch-UHD-Mirror-6047010
+
+OPTIONS_DEFINE= USRP1 USRP2
+OPTIONS_DEFAULT= USRP1 USRP2
+USRP1_DESC= Build Ettus USRP1 firmware
+USRP2_DESC= Build Ettus USRP2 firmware
+
+.include <bsd.port.pre.mk>
+
+.if ${OSVERSION} < 800000
+IGNORE= needs libusb 1.0
+.endif
+
+.if ${PORT_OPTIONS:MDOCS}
+BUILD_DEPENDS+= doxygen:${PORTSDIR}/devel/doxygen
+CMAKE_ARGS+= -DENABLE_DOXYGEN:STRING="ON"
+HAVEDOCS= YES
+.endif
+
+.if ${PORT_OPTIONS:MUSRP1}
+BUILD_DEPENDS+= sdcc:${PORTSDIR}/lang/sdcc
+USRP1= YES
+PLIST_SUB+= PUSRP1=""
+.else
+PLIST_SUB+= PUSRP1="@comment "
+.endif
+
+.if ${PORT_OPTIONS:MUSRP2}
+BUILD_DEPENDS+= ${LOCALBASE}/zpu/bin/zpu-elf-gcc:${PORTSDIR}/devel/zpu-gcc \
+ ${LOCALBASE}/zpu/bin/zpu-elf-as:${PORTSDIR}/devel/zpu-binutils
+USRP2= YES
+PLIST_SUB+= PUSRP2=""
+.else
+PLIST_SUB+= PUSRP2="@comment "
+.endif
+
+do-configure:
+# Configure the cmake portion of the host build
+ ${MKDIR} ${CONFIGURE_WRKSRC}
+ cd ${CONFIGURE_WRKSRC}; ${SETENV} ${CMAKE_ENV} \
+ ${CMAKE_BIN} ${CMAKE_ARGS} ${WRKSRC}/host
+
+do-build:
+# build host component
+ (export PATH=${LOCALBASE}/zpu/bin:${PATH};cd ${CONFIGURE_WRKSRC}&&${GMAKE})
+# build usrp firmware
+# (export PATH=${LOCALBASE}/zpu/bin:${PATH};\
+# cd ${WRKSRC}/images && ${GMAKE} -f Makefile images)
+
+.if USRP1
+ (cd ${WRKSRC}/images && ${GMAKE} -f Makefile images_usrp1)
+.endif
+.if USRP2
+ (export PATH=${LOCALBASE}/zpu/bin:${PATH};\
+ cd ${WRKSRC}/images && ${GMAKE} -f Makefile images_usrp2)
+.endif
+
+do-install:
+# install host component
+ cd ${CONFIGURE_WRKSRC} && ${MAKE} install
+# install usrp firmware
+ ${MKDIR} ${PREFIX}/share/uhd
+ ${MKDIR} ${PREFIX}/share/uhd/images
+
+.if USRP2
+.for f in usrp_n200_fw.bin usrp2_fw.bin \
+ usrp_n210_fw.bin
+ ${INSTALL_DATA} ${WRKSRC}/images/images/${f} ${PREFIX}/share/uhd/images/$f
+.endfor
+.endif
+
+.if USRP1
+.for f in usrp1_fw.ihx usrp1_fpga.rbf usrp1_fpga_4rx.rbf usrp_b100_fw.ihx
+ ${INSTALL_DATA} ${WRKSRC}/images/images/${f} ${PREFIX}/share/uhd/images/$f
+.endfor
+ ${MKDIR} ${PREFIX}/share/uhd/fpga/usrp1/rev2
+ ${INSTALL_DATA} ${WRKSRC}/fpga/usrp1/rbf/rev2/*.rbf \
+ ${PREFIX}/share/uhd/fpga/usrp1/rev2
+ ${MKDIR} ${PREFIX}/share/uhd/fpga/usrp1/rev4
+ ${INSTALL_DATA} ${WRKSRC}/fpga/usrp1/rbf/rev4/*.rbf \
+ ${PREFIX}/share/uhd/fpga/usrp1/rev4
+.endif
+
+post-install:
+ ${ECHO_MSG} fpga and firmware installed in /usr/local/share/uhd
+.if HAVEDOCS
+ ${ECHO_MSG} docs installed in /usr/local/share/doc/uhd
+.endif
+
+.include <bsd.port.post.mk>
Added: head/comms/usrp/distinfo
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/distinfo Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,2 @@
+SHA256 (Ettus-USRP-3.4.3.tar.gz) = 536b3b1ba7c9bb1b7c87c197708083b47efb3b3cdc14b841230f093fa915961b
+SIZE (Ettus-USRP-3.4.3.tar.gz) = 6215038
Added: head/comms/usrp/files/patch-firmware_fx2_CMakeLists.txt
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_CMakeLists.txt Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,20 @@
+--- firmware/fx2/CMakeLists.txt.orig 2012-07-30 14:09:48.000000000 -0500
++++ firmware/fx2/CMakeLists.txt 2012-10-27 08:07:39.000000000 -0500
+@@ -25,13 +25,16 @@
+ # Set toolchain to use SDCC
+ ########################################################################
+ # we're doing mixed ASM and C
+-ENABLE_LANGUAGE(ASM_SDCC)
++ENABLE_LANGUAGE(ASM_SDCC OPTIONAL)
++
++#SET(CMAKE_ASM_SDCC_COMPILER /usr/local/bin/sdcc)
+
+ ########################################################################
+ # C flags and linking flags
+ ########################################################################
+ ADD_DEFINITIONS(-DHAVE_USRP2)
+ set(CMAKE_C_LINK_FLAGS "--code-loc 0x0000 --code-size 0x1800 --xram-loc 0x1800 --xram-size 0x0800 -Wl '-b USBDESCSEG = 0xE000'")
++set(C_DEFINES "--code-loc 0x0000 --code-size 0x1800 --xram-loc 0x1800 --xram-size 0x0800 -Wl '-b USBDESCSEG = 0xE000'")
+ set(CMAKE_C_FLAGS "--no-xinit-opt")
+
+ ########################################################################
Added: head/comms/usrp/files/patch-firmware_fx2_b100_CMakeLists.txt
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_CMakeLists.txt Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,11 @@
+--- firmware/fx2/b100/CMakeLists.txt.orig 2012-10-10 16:53:23.000000000 -0500
++++ firmware/fx2/b100/CMakeLists.txt 2012-10-10 16:53:31.000000000 -0500
+@@ -66,7 +66,7 @@
+
+ set_source_files_properties(
+ ${CMAKE_CURRENT_SOURCE_DIR}/usrp_main.c
+- PROPERTIES COMPILE_FLAGS "--std-sdcc99 --opt-code-speed --fommit-frame-pointer"
++ PROPERTIES COMPILE_FLAGS "--std-sdcc99 --opt-code-speed --fomit-frame-pointer"
+ )
+
+ add_executable(b100_fw ${b100_sources})
Added: head/comms/usrp/files/patch-firmware_fx2_b100_board_specific.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_board_specific.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,11 @@
+--- firmware/fx2/b100/board_specific.c.orig 2012-10-10 13:42:54.000000000 -0500
++++ firmware/fx2/b100/board_specific.c 2012-10-10 13:43:04.000000000 -0500
+@@ -58,7 +58,7 @@
+ // NOP on usrp1
+ }
+
+-static xdata unsigned char xbuf[1];
++static __xdata unsigned char xbuf[1];
+
+ void
+ init_board (void)
Added: head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,29 @@
+--- firmware/fx2/b100/eeprom_io.c.orig 2012-10-10 13:40:13.000000000 -0500
++++ firmware/fx2/b100/eeprom_io.c 2012-10-10 13:40:39.000000000 -0500
+@@ -27,12 +27,12 @@
+ // returns non-zero if successful, else 0
+ unsigned char
+ eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
+- xdata unsigned char *buf, unsigned char len)
++ __xdata unsigned char *buf, unsigned char len)
+ {
+ // We setup a random read by first doing a "zero byte write".
+ // Writes carry an address. Reads use an implicit address.
+
+- static xdata unsigned char cmd[1];
++ static __xdata unsigned char cmd[1];
+ cmd[0] = eeprom_offset;
+ if (!i2c_write(i2c_addr, cmd, 1))
+ return 0;
+@@ -46,9 +46,9 @@
+ // returns non-zero if successful, else 0
+ unsigned char
+ eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
+- const xdata unsigned char *buf, unsigned char len)
++ const __xdata unsigned char *buf, unsigned char len)
+ {
+- static xdata unsigned char cmd[2];
++ static __xdata unsigned char cmd[2];
+ unsigned char ok;
+
+ while (len-- > 0){
Added: head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.h Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,17 @@
+--- firmware/fx2/b100/eeprom_io.h.orig 2012-10-10 16:55:20.000000000 -0500
++++ firmware/fx2/b100/eeprom_io.h 2012-10-10 16:55:36.000000000 -0500
+@@ -27,12 +27,12 @@
+ // returns non-zero if successful, else 0
+ unsigned char
+ eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
+- xdata unsigned char *buf, unsigned char len);
++ __xdata unsigned char *buf, unsigned char len);
+
+ // returns non-zero if successful, else 0
+ unsigned char
+ eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
+- const xdata unsigned char *buf, unsigned char len);
++ const __xdata unsigned char *buf, unsigned char len);
+
+
+ #endif /* INCLUDED_EEPROM_IO_H */
Added: head/comms/usrp/files/patch-firmware_fx2_b100_fpga_load.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_fpga_load.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,40 @@
+--- firmware/fx2/b100/fpga_load.c.orig 2012-10-10 13:41:50.000000000 -0500
++++ firmware/fx2/b100/fpga_load.c 2012-10-10 16:37:38.000000000 -0500
+@@ -82,9 +82,9 @@
+ #else
+
+ static void
+-clock_out_config_byte (unsigned char bits) _naked
++clock_out_config_byte (unsigned char bits) __naked
+ {
+- _asm
++ __asm
+ mov a, dpl
+
+ rlc a
+@@ -129,14 +129,14 @@
+
+ ret
+
+- _endasm;
++ __endasm;
+ }
+
+ #endif
+
+ static void
+ clock_out_bytes (unsigned char bytecount,
+- unsigned char xdata *p)
++ unsigned char __xdata *p)
+ {
+ while (bytecount-- > 0)
+ clock_out_config_byte (*p++);
+@@ -156,7 +156,7 @@
+ * ALTERA_NSTATUS = 1 (input)
+ */
+ unsigned char
+-fpga_load_xfer (xdata unsigned char *p, unsigned char bytecount)
++fpga_load_xfer (__xdata unsigned char *p, unsigned char bytecount)
+ {
+ clock_out_bytes (bytecount, p);
+ return 1;
Added: head/comms/usrp/files/patch-firmware_fx2_b100_fpga_rev2.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_fpga_rev2.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,18 @@
+--- firmware/fx2/b100/fpga_rev2.c.orig 2012-10-10 13:42:24.000000000 -0500
++++ firmware/fx2/b100/fpga_rev2.c 2012-10-10 13:42:45.000000000 -0500
+@@ -29,13 +29,13 @@
+ unsigned char g_rx_reset = 0;
+
+ void
+-fpga_write_reg (unsigned char regno, const xdata unsigned char *regval)
++fpga_write_reg (unsigned char regno, const __xdata unsigned char *regval)
+ {
+ //nop
+ }
+
+
+-static xdata unsigned char regval[4] = {0, 0, 0, 0};
++static __xdata unsigned char regval[4] = {0, 0, 0, 0};
+
+ // Resets both AD9862's and the FPGA serial bus interface.
+
Added: head/comms/usrp/files/patch-firmware_fx2_b100_gpif.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_gpif.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,29 @@
+--- firmware/fx2/b100/gpif.c.orig 2012-10-10 13:39:33.000000000 -0500
++++ firmware/fx2/b100/gpif.c 2012-10-10 13:39:56.000000000 -0500
+@@ -156,7 +156,7 @@
+ // END DO NOT EDIT
+
+ // DO NOT EDIT ...
+-const char xdata WaveData[128] =
++const char __xdata WaveData[128] =
+ {
+ // Wave 0
+ /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
+@@ -182,7 +182,7 @@
+ // END DO NOT EDIT
+
+ // DO NOT EDIT ...
+-const char xdata FlowStates[36] =
++const char __xdata FlowStates[36] =
+ {
+ /* Wave 0 FlowStates */ 0x81,0x2D,0x0E,0x00,0x00,0x04,0x03,0x02,0x00,
+ /* Wave 1 FlowStates */ 0x81,0x2D,0x09,0x00,0x00,0x04,0x03,0x02,0x00,
+@@ -192,7 +192,7 @@
+ // END DO NOT EDIT
+
+ // DO NOT EDIT ...
+-const char xdata InitData[7] =
++const char __xdata InitData[7] =
+ {
+ /* Regs */ 0xA0,0x00,0x00,0x00,0xEE,0x4E,0x00
+ };
Added: head/comms/usrp/files/patch-firmware_fx2_b100_usrp_main.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_usrp_main.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,39 @@
+--- firmware/fx2/b100/usrp_main.c.orig 2012-10-10 13:41:00.000000000 -0500
++++ firmware/fx2/b100/usrp_main.c 2012-10-10 16:35:30.000000000 -0500
+@@ -54,14 +54,14 @@
+ unsigned char g_rx_enable = 0;
+ unsigned char g_rx_overrun = 0;
+ unsigned char g_tx_underrun = 0;
+-bit enable_gpif = 0;
++__bit enable_gpif = 0;
+
+ /*
+ * the host side fpga loader code pushes an MD5 hash of the bitstream
+ * into hash1.
+ */
+ #define USRP_HASH_SIZE 16
+-xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
++__xdata __at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
+
+ //void clear_fpga_data_fifo(void);
+
+@@ -220,7 +220,7 @@
+ * Toggle led 0
+ */
+ void
+-isr_tick (void) interrupt
++isr_tick (void) __interrupt
+ {
+ static unsigned char count = 1;
+
+@@ -239,8 +239,8 @@
+ void
+ patch_usb_descriptors(void)
+ {
+- static xdata unsigned char hw_rev;
+- static xdata unsigned char serial_no[SERIAL_NO_LEN];
++ static __xdata unsigned char hw_rev;
++ static __xdata unsigned char serial_no[SERIAL_NO_LEN];
+ unsigned char i;
+
+ eeprom_read(I2C_ADDR_BOOT, HW_REV_OFFSET, &hw_rev, 1); // LSB of device id
Added: head/comms/usrp/files/patch-firmware_fx2_b100_usrp_regs.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_b100_usrp_regs.h Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,18 @@
+--- firmware/fx2/b100/usrp_regs.h.orig 2012-10-10 16:32:04.000000000 -0500
++++ firmware/fx2/b100/usrp_regs.h 2012-10-10 16:33:34.000000000 -0500
+@@ -59,11 +59,11 @@
+ #define PORT_A_ADDR 0x80
+ #define PORT_C_ADDR 0xA0
+
+-sbit at PORT_A_ADDR+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A
+-sbit at PORT_A_ADDR+1 bitALTERA_NCONFIG;
+-sbit at PORT_A_ADDR+3 bitALTERA_DATA0;
++__sbit __at PORT_A_ADDR+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A
++__sbit __at PORT_A_ADDR+1 bitALTERA_NCONFIG;
++__sbit __at PORT_A_ADDR+3 bitALTERA_DATA0;
+
+-sbit at PORT_C_ADDR+7 bitALTERA_CONF_DONE;
++__sbit __at PORT_C_ADDR+7 bitALTERA_CONF_DONE;
+
+
+ /* Port B: GPIF FD[7:0] */
Added: head/comms/usrp/files/patch-firmware_fx2_common_delay.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_common_delay.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,40 @@
+--- firmware/fx2/common/delay.c.orig 2012-07-30 14:09:48.000000000 -0500
++++ firmware/fx2/common/delay.c 2012-10-07 19:36:36.000000000 -0500
+@@ -24,11 +24,12 @@
+ * Delay approximately 1 microsecond (including overhead in udelay).
+ */
+ static void
+-udelay1 (void) _naked
++udelay1 (void)
++//__naked
+ {
+- _asm ; lcall that got us here took 4 bus cycles
++ __asm ; lcall that got us here took 4 bus cycles
+ ret ; 4 bus cycles
+- _endasm;
++ __endasm;
+ }
+
+ /*
+@@ -51,9 +52,10 @@
+ * but explains the factor of 4 problem below).
+ */
+ static void
+-mdelay1 (void) _naked
++mdelay1 (void)
++// _naked
+ {
+- _asm
++ __asm
+ mov dptr,#(-1200 & 0xffff)
+ 002$:
+ inc dptr ; 3 bus cycles
+@@ -62,7 +64,7 @@
+ jnz 002$ ; 3 bus cycles
+
+ ret
+- _endasm;
++ __endasm;
+ }
+
+ void
Added: head/comms/usrp/files/patch-firmware_fx2_common_eeprom_init.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_common_eeprom_init.c Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,11 @@
+--- firmware/fx2/common/eeprom_init.c.orig 2012-07-30 14:09:48.000000000 -0500
++++ firmware/fx2/common/eeprom_init.c 2012-10-07 20:10:02.000000000 -0500
+@@ -28,7 +28,7 @@
+ * into hash1.
+ */
+ #define USRP_HASH_SIZE 16
+-xdata at USRP_HASH_SLOT_0_ADDR unsigned char hash0[USRP_HASH_SIZE];
++__xdata __at USRP_HASH_SLOT_0_ADDR unsigned char hash0[USRP_HASH_SIZE];
+
+
+ #define REG_RX_PWR_DN 1
Added: head/comms/usrp/files/patch-firmware_fx2_common_fpga_load.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_common_fpga_load.h Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,11 @@
+--- firmware/fx2/common/fpga_load.h.orig 2012-07-30 14:09:48.000000000 -0500
++++ firmware/fx2/common/fpga_load.h 2012-10-07 19:38:19.000000000 -0500
+@@ -22,7 +22,7 @@
+ #define INCLUDED_FPGA_LOAD_H
+
+ unsigned char fpga_load_begin (void);
+-unsigned char fpga_load_xfer (xdata unsigned char *p, unsigned char len);
++unsigned char fpga_load_xfer (__xdata unsigned char *p, unsigned char len);
+ unsigned char fpga_load_end (void);
+
+ #endif /* INCLUDED_FPGA_LOAD_H */
Added: head/comms/usrp/files/patch-firmware_fx2_common_fx2regs.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/comms/usrp/files/patch-firmware_fx2_common_fx2regs.h Sun Dec 9 19:43:02 2012 (r308558)
@@ -0,0 +1,821 @@
+--- firmware/fx2/common/fx2regs.h.orig 2012-07-30 14:09:48.000000000 -0500
++++ firmware/fx2/common/fx2regs.h 2012-10-10 13:21:13.000000000 -0500
+@@ -48,22 +48,22 @@
+ // The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
+ // address allocation by using "#define ALLOCATE_EXTERN".
+ // When using "#define ALLOCATE_EXTERN", you get (for instance):
+-// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
++// __xdata volatile BYTE OUT7BUF[64] __at 0x7B40;
+ // Such lines are created from FX2.h by using the preprocessor.
+ // Incidently, these lines will not generate any space in the resulting hex
+ // file; they just bind the symbols to the addresses for compilation.
+ // You just need to put "#define ALLOCATE_EXTERN" in your main program file;
+ // i.e. fw.c or a stand-alone C source file.
+ // Without "#define ALLOCATE_EXTERN", you just get the external reference:
+-// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
++// extern __xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
+ // This uses the concatenation operator "##" to insert a comment "//"
+-// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
++// to cut off the end of the line, "__at 0x7B40;", which is not wanted.
+ */
+
+
+ #ifdef ALLOCATE_EXTERN
+ #define EXTERN
+-#define _AT_(a) at a
++#define _AT_(a) __at a
+ #else
+ #define EXTERN extern
+ #define _AT_ ;/ ## /
+@@ -72,162 +72,162 @@
+ typedef unsigned char BYTE;
+ typedef unsigned short WORD;
+
+-EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
+-EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
++EXTERN __xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
++EXTERN __xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
+
+ // General Configuration
+
+-EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
+-EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
+-EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
+-EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
+-EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
+-EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
+-EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
+-EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
+-EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
+-EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
+-EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
+-EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
++EXTERN __xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
++EXTERN __xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
++EXTERN __xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
++EXTERN __xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
++EXTERN __xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
++EXTERN __xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
++EXTERN __xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
++EXTERN __xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
++EXTERN __xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
++EXTERN __xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
++EXTERN __xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
++EXTERN __xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
+
+ // Endpoint Configuration
+-EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
+-EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
+-EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
+-EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
+-EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
+-EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
+-EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
+-EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
+-EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
+-EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
+-EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
+-EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
+-EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
+-EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
+-EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
+-EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
+-EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
+-EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
+-EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
+-EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
+-EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
+-EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
+-EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
+-EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
+-EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
+-EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
+-EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
+-EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
+-EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
+-EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
+-EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
+-EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
++EXTERN __xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
++EXTERN __xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
++EXTERN __xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
++EXTERN __xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
++EXTERN __xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
++EXTERN __xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
++EXTERN __xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
++EXTERN __xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
++EXTERN __xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
++EXTERN __xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
++EXTERN __xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
++EXTERN __xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
++EXTERN __xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
++EXTERN __xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
++EXTERN __xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
++EXTERN __xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
++EXTERN __xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
++EXTERN __xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
++EXTERN __xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
++EXTERN __xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
++EXTERN __xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
++EXTERN __xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
++EXTERN __xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
++EXTERN __xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
++EXTERN __xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
++EXTERN __xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
++EXTERN __xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
++EXTERN __xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
++EXTERN __xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
++EXTERN __xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
++EXTERN __xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
++EXTERN __xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
+
+ // Interrupts
+
+-EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
+-EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
+-EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
+-EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
+-EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
+-EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
+-EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
+-EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
+-EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
+-EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
+-EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
+-EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
+-EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
+-EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
+-EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
+-EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
+-EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
+-EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
+-EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
+-EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
+-EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
+-EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
+-EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
+-EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
+-EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
++EXTERN __xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
++EXTERN __xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
++EXTERN __xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
++EXTERN __xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
++EXTERN __xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
++EXTERN __xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
++EXTERN __xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
++EXTERN __xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
++EXTERN __xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
++EXTERN __xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
++EXTERN __xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
++EXTERN __xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
++EXTERN __xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
++EXTERN __xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
++EXTERN __xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
++EXTERN __xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
++EXTERN __xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
++EXTERN __xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
++EXTERN __xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
++EXTERN __xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
++EXTERN __xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
++EXTERN __xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
++EXTERN __xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
++EXTERN __xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
++EXTERN __xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
+
+ // Input/Output
+
+-EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
+-EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
+-EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
+-EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
+-EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
+-EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
+-EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
+-EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
++EXTERN __xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
++EXTERN __xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
++EXTERN __xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
++EXTERN __xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
++EXTERN __xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
++EXTERN __xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
++EXTERN __xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
++EXTERN __xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
+
+ #define EXTAUTODAT1 XAUTODAT1
+ #define EXTAUTODAT2 XAUTODAT2
+
+ // USB Control
+
+-EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
+-EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
+-EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
+-EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
+-EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
+-EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
+-EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
+-EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
++EXTERN __xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
++EXTERN __xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
++EXTERN __xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
++EXTERN __xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
++EXTERN __xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
++EXTERN __xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
++EXTERN __xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
++EXTERN __xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
+
+ // Endpoints
+
+-EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
+-EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
+-EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
+-EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
+-EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
+-EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
+-EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
+-EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
+-EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
+-EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
+-EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
+-EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
+-EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
+-EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
+-EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
+-EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
+-EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
+-EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
+-EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
+-EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
+-EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
+-EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
+-EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
+-EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
+-EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
+-EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
+-EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
+-EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
+-EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
+-EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
+-EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
+-EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
+-EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
+-EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
+-EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
++EXTERN __xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
++EXTERN __xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
++EXTERN __xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
++EXTERN __xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
++EXTERN __xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
++EXTERN __xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
++EXTERN __xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
++EXTERN __xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
++EXTERN __xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
++EXTERN __xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
++EXTERN __xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
++EXTERN __xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
++EXTERN __xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
++EXTERN __xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
++EXTERN __xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
++EXTERN __xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
++EXTERN __xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
++EXTERN __xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
++EXTERN __xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
++EXTERN __xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
++EXTERN __xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
++EXTERN __xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
++EXTERN __xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
++EXTERN __xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
++EXTERN __xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
++EXTERN __xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
++EXTERN __xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
++EXTERN __xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
++EXTERN __xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
++EXTERN __xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
++EXTERN __xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
++EXTERN __xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
++EXTERN __xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
++EXTERN __xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
++EXTERN __xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
+
+ // GPIF
+
+-EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
+-EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
+-EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
+-EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
+-EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
+-EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
+-
+-EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
+-EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
+-EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
+-EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
++EXTERN __xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
++EXTERN __xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
++EXTERN __xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
++EXTERN __xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
++EXTERN __xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
++EXTERN __xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
++
++EXTERN __xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
++EXTERN __xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
++EXTERN __xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
++EXTERN __xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
+
+ #define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+ #define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+@@ -238,68 +238,68 @@
+ #define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+ #define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+
+-// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
+-// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
+-EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
+-EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
+-EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
+-// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
+-// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
+-EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
+-EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
+-EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
+-// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
+-// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
+-EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
+-EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
+-EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
+-// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
+-// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
+-EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
+-EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
+-EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
+-EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
+-EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
+-EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
+-EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
+-EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
+-EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
++// EXTERN __xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
++// EXTERN __xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
++EXTERN __xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
++EXTERN __xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
++EXTERN __xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
++// EXTERN __xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
++// EXTERN __xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
++EXTERN __xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
++EXTERN __xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
++EXTERN __xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
++// EXTERN __xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
++// EXTERN __xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
++EXTERN __xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
++EXTERN __xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
++EXTERN __xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
++// EXTERN __xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
++// EXTERN __xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
++EXTERN __xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
++EXTERN __xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
++EXTERN __xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
++EXTERN __xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
++EXTERN __xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
++EXTERN __xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
++EXTERN __xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
++EXTERN __xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
++EXTERN __xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
+
+ // UDMA
+
+-EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
+-EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
+-EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
+-EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
+-EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
+-EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
+-EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
+-EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
+-EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
+-EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
+-EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
+-EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
++EXTERN __xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
++EXTERN __xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
++EXTERN __xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
++EXTERN __xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
++EXTERN __xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
++EXTERN __xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
++EXTERN __xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
++EXTERN __xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
++EXTERN __xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
++EXTERN __xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
++EXTERN __xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
++EXTERN __xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
+
+
+ // Debug/Test
+
+-EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
+-EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
+-EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
+-EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
+-EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
+-EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
+-EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
++EXTERN __xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
++EXTERN __xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
++EXTERN __xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
++EXTERN __xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
++EXTERN __xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
++EXTERN __xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
++EXTERN __xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
+
+ // Endpoint Buffers
+
+-EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
+-EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
+-EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
+-EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
+-EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
+-EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
+-EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
++EXTERN __xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
++EXTERN __xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
++EXTERN __xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
++EXTERN __xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
++EXTERN __xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
++EXTERN __xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
++EXTERN __xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
+
+ #undef EXTERN
+ #undef _AT_
+@@ -312,201 +312,201 @@
+ "ezregs.inc" which includes the same basic information for assembly inclusion.
+ -----------------------------------------------------------------------------*/
+
+-sfr at 0x80 IOA;
+-sfr at 0x81 SP;
+-sfr at 0x82 DPL;
+-sfr at 0x83 DPH;
+-sfr at 0x84 DPL1;
+-sfr at 0x85 DPH1;
+-sfr at 0x86 DPS;
++__sfr __at 0x80 IOA;
++__sfr __at 0x81 SP;
++__sfr __at 0x82 DPL;
++__sfr __at 0x83 DPH;
++__sfr __at 0x84 DPL1;
++__sfr __at 0x85 DPH1;
++__sfr __at 0x86 DPS;
+ /* DPS */
+- sbit at 0x86+0 SEL;
+-sfr at 0x87 PCON; /* PCON */
++ __sbit __at 0x86+0 SEL;
++__sfr __at 0x87 PCON; /* PCON */
+ //sbit IDLE = 0x87+0;
+ //sbit STOP = 0x87+1;
+ //sbit GF0 = 0x87+2;
+ //sbit GF1 = 0x87+3;
+ //sbit SMOD0 = 0x87+7;
+-sfr at 0x88 TCON;
++__sfr __at 0x88 TCON;
+ /* TCON */
+- sbit at 0x88+0 IT0;
+- sbit at 0x88+1 IE0;
+- sbit at 0x88+2 IT1;
+- sbit at 0x88+3 IE1;
+- sbit at 0x88+4 TR0;
+- sbit at 0x88+5 TF0;
+- sbit at 0x88+6 TR1;
+- sbit at 0x88+7 TF1;
+-sfr at 0x89 TMOD;
++ __sbit __at 0x88+0 IT0;
++ __sbit __at 0x88+1 IE0;
++ __sbit __at 0x88+2 IT1;
++ __sbit __at 0x88+3 IE1;
++ __sbit __at 0x88+4 TR0;
++ __sbit __at 0x88+5 TF0;
++ __sbit __at 0x88+6 TR1;
++ __sbit __at 0x88+7 TF1;
++__sfr __at 0x89 TMOD;
+ /* TMOD */
+- //sbit M00 = 0x89+0;
+- //sbit M10 = 0x89+1;
+- //sbit CT0 = 0x89+2;
+- //sbit GATE0 = 0x89+3;
+- //sbit M01 = 0x89+4;
+- //sbit M11 = 0x89+5;
+- //sbit CT1 = 0x89+6;
+- //sbit GATE1 = 0x89+7;
+-sfr at 0x8A TL0;
+-sfr at 0x8B TL1;
+-sfr at 0x8C TH0;
+-sfr at 0x8D TH1;
+-sfr at 0x8E CKCON;
++ //__sbit M00 = 0x89+0;
++ //__sbit M10 = 0x89+1;
++ //__sbit CT0 = 0x89+2;
++ //__sbit GATE0 = 0x89+3;
++ //__sbit M01 = 0x89+4;
++ //__sbit M11 = 0x89+5;
++ //__sbit CT1 = 0x89+6;
++ //__sbit GATE1 = 0x89+7;
++__sfr __at 0x8A TL0;
++__sfr __at 0x8B TL1;
++__sfr __at 0x8C TH0;
++__sfr __at 0x8D TH1;
++__sfr __at 0x8E CKCON;
+ /* CKCON */
+- //sbit MD0 = 0x89+0;
+- //sbit MD1 = 0x89+1;
+- //sbit MD2 = 0x89+2;
+- //sbit T0M = 0x89+3;
+- //sbit T1M = 0x89+4;
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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