PERFORCE change 601761 for review

[Robert Watson]

http://p4web.freebsd.org/@@601761?ac=10

Change 601761 by rwatson at rwatson_zenith_cl_cam_ac_uk on 2013/09/06 11:05:45

	Fixes to the CHERI CCall/CReturn stub exception handler:
	
	(1) Set noorder -- exception handlers with NOPs semi-arbitrarily
	    inserted and removed work less well.
	
	(2) No need to ifdef CHERI exception handling paths -- this is
	    definitely compiled only for CHERI.
	
	(3) Insert several NOPs after modifying EPC to ensure the new
	    value is in place before ERET.
	
	The no-op CCall/CReturn handler now appears to be a no-op, rather
	than a recipe for segfaults.

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/bin/cheritest/cheritest.c#13 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/ccall.S#3 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/bin/cheritest/cheritest.c#13 (text+ko) ====


==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/ccall.S#3 (text+ko) ====

@@ -43,6 +43,8 @@
 
 #include "assym.s"
 
+	.set noreorder	/* Preserve nops, allow instructions in b-d slots. */
+
 /*
  * Software implementations of CCall, CReturn handlers for CHERI.
  *
@@ -51,18 +53,15 @@
 VECTOR(CHERICCallVector, unknown)
         .set push
         .set noat
-#ifdef CPU_CHERI
         CHERI_EXCEPTION_ENTER(k0)
-#endif
 
 	/* XXXRW: For now, increment PC as though it were a no-op. */
         MFC0	k0, MIPS_COP_0_EXC_PC
 	PTR_ADDU	k0, 4
 	MTC0	k0, MIPS_COP_0_EXC_PC
+	COP0_SYNC
 
-#ifdef CPU_CHERI
 	CHERI_EXCEPTION_RETURN(k0)
-#endif
 	eret
         .set pop
 VECTOR_END(CHERICCallVector)