PERFORCE change 228019 for review

[Bjoern A. Zeeb]

http://p4web.freebsd.org/@@228019?ac=10

Change 228019 by bz at bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM.
	
	Tested by:		jdw57
	Hardware changes in:	r6828

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/conf/options.mips#9 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/std.beri#5 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cpufunc.h#7 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cpu.c#4 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/conf/options.mips#9 (text+ko) ====

@@ -79,6 +79,11 @@
 OCTEON_BOARD_CAPK_0100ND	opt_cvmx.h
 
 #
+# Options specific to the BERI and CHERI CPUs.
+#
+BERI_LARGE_TLB			opt_global.h
+
+#
 # Options that control the Atheros SoC peripherals
 #
 ARGE_DEBUG			opt_arge.h

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/std.beri#5 (text+ko) ====

@@ -2,3 +2,6 @@
 files	"../beri/files.beri"
 
 cpu		CPU_MIPS4KC
+
+options 	BERI_LARGE_TLB
+

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cpufunc.h#7 (text+ko) ====

@@ -242,8 +242,13 @@
 #ifdef CPU_CNMIPS
 MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
 #endif
+#ifdef BERI_LARGE_TLB
+MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
+#endif
+#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
+MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
+#endif
 #ifdef CPU_NLM
-MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
 #endif
 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cpu.c#4 (text+ko) ====

@@ -99,17 +99,29 @@
 
 	/* Learn TLB size and L1 cache geometry. */
 	cfg1 = mips_rd_config1();
-#ifndef CPU_NLM
-	cpuinfo->tlb_nentries = 
-	    ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
-#else
+
+#if defined(CPU_NLM)
 	/* Account for Extended TLB entries in XLP */
 	tmp = mips_rd_config6();
 	cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
+#elif defined(BERI_LARGE_TLB)
+	/* Check if we support extended TLB entries and if so activate. */
+	tmp = mips_rd_config5();
+#define	BERI_CP5_LTLB_SUPPORTED	0x1
+	if (tmp & BERI_CP5_LTLB_SUPPORTED) {
+		/* See how many extra TLB entries we have. */
+		tmp = mips_rd_config6();
+		cpuinfo->tlb_nentries = (tmp >> 16) + 1;
+		/* Activate the extended entries. */
+		mips_wr_config6(tmp|0x4);
+	} else
+#endif
+#if !defined(CPU_NLM)
+	cpuinfo->tlb_nentries = 
+	    ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
 #endif
-
+#if defined(CPU_CNMIPS)
 	/* Add extended TLB size information from config4.  */
-#if defined(CPU_CNMIPS)
 	cfg4 = mips_rd_config4();
 	if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
 		cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;