PERFORCE change 218927 for review

[Robert Watson]

http://p4web.freebsd.org/@@218927?ac=10

Change 218927 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/10/22 21:22:46

	Now that immediate-indexed notation is supported for CHERI CLC and
	CSC, use it.  It's not quite the syntax documented in the manual,
	but it still allows us to lose assertions that immediate offsets are
	0, which will improve context switch code significantly.

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#8 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#8 (text+ko) ====

@@ -153,24 +153,12 @@
 /*
  * Capability store; while this doesn't muck with c0, it does require a memory
  * clobber.
- *
- * XXXRW: The assembler does not yet support base+offset, just base, so assert
- * that offset (for now) is not permitted.
  */
-#ifdef _KERNEL
 #define	CHERI_CSC(cs, cb, regbase, offset) do {				\
-	KASSERT((offset) == 0,						\
-	    ("CHERI_CSC: non-zero offset not supported"));		\
-	__asm__ __volatile__ ("csc $c%0, %1($c%2)" : :			\
-	    "i" (cs), "r" (regbase), "i" (cb) : "memory");		\
+	__asm__ __volatile__ ("csc $c%0, %1, %2($c%3)" : :		\
+	    "i" (cs), "r" (regbase), "i" (offset), "i" (cb) :		\
+	    "memory");							\
 } while (0)
-#else
-#define	CHERI_CSC(cs, cb, regbase, offset) do {				\
-	assert((offset) == 0);						\
-	__asm__ __volatile__ ("csc $c%0, %1($c%2)" : :			\
-	    "i" (cs), "r" (regbase), "i" (cb) : "memory");		\
-} while (0)
-#endif
 
 /*
  * Routines that modify or replace values in capability registers, and that if
@@ -233,32 +221,15 @@
 		    "i" (cd), "i" (cb), "r" (v));			\
 } while (0)
 
-/*
- * XXXRW: The assembler does not yet support base+offset, just base, so assert
- * that offset (for now) is not permitted.
- */
-#ifdef _KERNEL
 #define	CHERI_CLC(cd, cb, regbase, offset) do {				\
-	KASSERT((offset) == 0,						\
-	    ("CHERI_CLC: non-zero offset not supported"));		\
 	if ((cd) == 0)							\
-		__asm__ __volatile__ ("clc $c%0, %1($c%2)" : :		\
-		    "i" (cd), "r" (regbase), "i" (cb) : "memory");	\
+		__asm__ __volatile__ ("clc $c%0, %1, %2($c%3)" : :	\
+		    "i" (cd), "r" (regbase), "i" (offset), "i" (cb) :	\
+		    "memory");						\
 	else								\
-		__asm__ __volatile__ ("clc $c%0, %1($c%2)" : :		\
-		    "i" (cd), "r" (regbase), "i" (cb));			\
+		__asm__ __volatile__ ("clc $c%0, %1, %2($c%3)" : :	\
+		    "i" (cd), "r" (regbase), "i" (offset), "i" (cb));	\
 } while (0)
-#else
-#define	CHERI_CLC(cd, cb, regbase, offset) do {				\
-	assert((offset) == 0);						\
-	if ((cd) == 0)							\
-		__asm__ __volatile__ ("clc $c%0, %1($c%2)" : :		\
-		    "i" (cd), "r" (regbase), "i" (cb) : "memory");	\
-	else								\
-		__asm__ __volatile__ ("clc $c%0, %1($c%2)" : :		\
-		    "i" (cd), "r" (regbase), "i" (cb));			\
-} while (0)
-#endif
 
 static inline void
 cp2_capability_load(u_int crn_to, struct chericap *cp)