PERFORCE change 218755 for review
Robert Watson
rwatson at FreeBSD.org
Mon Oct 22 06:35:06 UTC 2012
http://p4web.freebsd.org/@@218755?ac=10
Change 218755 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/10/19 14:30:57
Merge CHERI ISAv2 support from the CHERI binutils tree to the CheriBSD
Perforce branch:
commit 664853aff8d01d9c8e03545136e80f6640960363
Author: Michael Roe <mroe at cornstalk.org.uk>
Date: Wed Oct 10 13:19:09 2012 +0100
Updated gas to version 2 of the CHERI ISA.
Affected files ...
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#4 edit
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#3 edit
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#7 edit
Differences ...
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#4 (text+ko) ====
@@ -8429,6 +8429,7 @@
USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
case 'v': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
+ case 'x': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
c, opc->name, opc->args);
@@ -9058,7 +9059,8 @@
is a base register specification. */
assert (args[1] == 'b' || args[1] == '5'
|| args[1] == '-' || args[1] == '4'
- || (args[1] == '+' && args[2] == 'b'));
+ || (args[1] == '+' && args[2] == 'b')
+ || (args[1] == '+' && args[2] == 'w'));
if (*s == '\0')
return;
@@ -9222,6 +9224,7 @@
case 'w':
case 'b':
case 'v':
+ case 'x':
if (s[0] == '$' && s[1] == 'c' && ISDIGIT (s[2]))
{
c = *args;
@@ -9252,6 +9255,11 @@
INSERT_OPERAND (FD, *ip, regno);
continue;
}
+ else if (c == 'x')
+ {
+ INSERT_OPERAND (RS, *ip, regno);
+ continue;
+ }
}
else
as_bad (_("Invalid capability register number"));
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#3 (text+ko) ====
@@ -914,6 +914,10 @@
OP_MASK_FD);
break;
+ case 'x':
+ (*info->fprintf_func) (info->stream, "c%d", (l >> OP_SH_RS) &
+ OP_MASK_RS);
+ break;
case 'o':
delta = ((l >> OP_SH_CDELTA) & OP_MASK_CDELTA);
(*info->fprintf_func) (info->stream, "%d", delta);
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#7 (text+ko) ====
@@ -188,30 +188,58 @@
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
-{"cgetbase","t,+b", 0x48000001, 0xffe007ff, 0, 0, I1 },
-{"cgetlen", "t,+b", 0x48000000, 0xffe007ff, 0, 0, I1 },
-{"cgetleng","t,+b", 0x48000000, 0xffe007ff, 0, 0, I1 },
-{"cgetperm","t,+b", 0x48000006, 0xffe007ff, 0, 0, I1 },
-{"cgettype","t,+b", 0x48000002, 0xffe007ff, 0, 0, I1 },
-{"csettype","+w,+b,m", 0x48800002, 0xffe0003f, 0, 0, I1 },
-{"cincbase","+w,+b,m", 0x48800001, 0xffe0003f, 0, 0, I1 },
-{"cmove", "+w,+b", 0x48800001, 0xffe007ff, 0, 0, I1 },
-{"csetlen", "+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1 },
-{"candperm","+w,+b,m", 0x48800006, 0xffe0003f, 0, 0, I1 },
+{"cgetperm","t,+b", 0x48000000, 0xffe007ff, 0, 0, I1},
+{"cgettype","t,+b", 0x48000001, 0xffe007ff, 0, 0, I1},
+{"cgetbase","t,+b", 0x48000002, 0xffe007ff, 0, 0, I1},
+{"cgetlen", "t,+b", 0x48000003, 0xffe007ff, 0, 0, I1},
+{"cgettag", "t,+b", 0x48000005, 0xffe007ff, 0, 0, I1},
+{"cgetunsealed", "t,+b", 0x48000006, 0xffe007ff, 0, 0, I1},
+{"cgetpcc", "t(+b)", 0x48000007, 0xffe007ff, 0, 0, I1},
+{"candperm","+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1},
+{"csettype","+w,+b,m", 0x48800001, 0xffe0003f, 0, 0, I1},
+{"cincbase","+w,+b,m", 0x48800002, 0xffe0003f, 0, 0, I1},
+{"cmove", "+w,+b", 0x48800002, 0xffe007ff, 0, 0, I1},
+{"csetlen", "+w,+b,m", 0x48800003, 0xffe0003f, 0, 0, I1},
+{"ccleartag", "+w", 0x48800005, 0xffe0ffff, 0, 0, I1},
+{"csc", "+x,d(+w)", 0xf8000000, 0xfc0007ff, 0, 0, I1},
+{"clc", "+x,d(+w)", 0xd8000000, 0xfc0007ff, 0, 0, I1},
+
{"cscr", "+w,m(+b)", 0x49200000, 0xffe0003f, 0, 0, I1 },
{"clcr", "+w,m(+b)", 0x49400000, 0xffe0003f, 0, 0, I1 },
-{"clb", "t,+o(+b)", 0x4a000000, 0xffe00000,0, 0, I1 },
-{"clh", "t,+o(+b)", 0x4a200000, 0xffe00000, 0, 0, I1 },
-{"clw", "t,+o(+b)", 0x4a400000, 0xffe00000, 0, 0, I1 },
-{"cld", "t,+o(+b)", 0x4a600000, 0xffe00000, 0, 0, I1 },
+/* mask should be 0xfc000007. Because I don't have letters for the
+ * other register and offset argument, temporarily mask them.
+ * Hence mask of 0xfc0007ff.
+ */
+{"clbu", "v,d(+w)", 0xc8000000, 0xfc0007ff, 0, 0, I1},
+{"clhu", "v,d(+w)", 0xc8000001, 0xfc0007ff, 0, 0, I1},
+{"clwu", "v,d(+w)", 0xc8000002, 0xfc0007ff, 0, 0, I1},
+/* there is no cldu */
+{"clb", "v,d(+w)", 0xc8000004, 0xfc0007ff, 0, 0, I1},
+{"clh", "v,d(+w)", 0xc8000005, 0xfc0007ff, 0, 0, I1},
+{"clw", "v,d(+w)", 0xc8000006, 0xfc0007ff, 0, 0, I1},
+{"cld", "v,d(+w)", 0xc8000007, 0xfc0007ff, 0, 0, I1},
+
+{"csbh", "v,d(+w)", 0xe8000000, 0xfc0007ff, 0, 0, I1},
+{"cshh", "v,d(+w)", 0xe8000001, 0xfc0007ff, 0, 0, I1},
+{"cswh", "v,d(+w)", 0xe8000002, 0xfc0007ff, 0, 0, I1},
+/* there is no csdu */
+{"csb", "v,d(+w)", 0xe8000004, 0xfc0007ff, 0, 0, I1},
+{"csh", "v,d(+w)", 0xe8000005, 0xfc0007ff, 0, 0, I1},
+{"csw", "v,d(+w)", 0xe8000006, 0xfc0007ff, 0, 0, I1},
+{"csd", "v,d(+w)", 0xe8000007, 0xfc0007ff, 0, 0, I1},
+
+{"clbi", "t,+o(+b)", 0x4a000000, 0xffe00000,0, 0, I1 },
+{"clhi", "t,+o(+b)", 0x4a200000, 0xffe00000, 0, 0, I1 },
+{"clwi", "t,+o(+b)", 0x4a400000, 0xffe00000, 0, 0, I1 },
+{"cldi", "t,+o(+b)", 0x4a600000, 0xffe00000, 0, 0, I1 },
{"clbr", "t,m(+b)", 0x4a800000, 0xffe0003f, 0, 0, I1 },
{"clhr", "t,m(+b)", 0x4aa00000, 0xffe0003f, 0, 0, I1 },
{"clwr", "t,m(+b)", 0x4ac00000, 0xffe0003f, 0, 0, I1 },
{"cldr", "t,m(+b)", 0x4ae00000, 0xffe0003f, 0, 0, I1 },
-{"csb", "t,+o(+b)", 0x4b000000, 0xffe00000, 0, 0, I1 },
-{"csh", "t,+o(+b)", 0x4b200000, 0xffe00000, 0, 0, I1 },
-{"csw", "t,+o(+b)", 0x4b400000, 0xffe00000, 0, 0, I1 },
-{"csd", "t,+o(+b)", 0x4b600000, 0xffe00000, 0, 0, I1 },
+{"csbi", "t,+o(+b)", 0x4b000000, 0xffe00000, 0, 0, I1 },
+{"cshi", "t,+o(+b)", 0x4b200000, 0xffe00000, 0, 0, I1 },
+{"cswi", "t,+o(+b)", 0x4b400000, 0xffe00000, 0, 0, I1 },
+{"csdi", "t,+o(+b)", 0x4b600000, 0xffe00000, 0, 0, I1 },
{"csbr", "t,m(+b)", 0x4b800000, 0xffe0003f, 0, 0, I1 },
{"cshr", "t,m(+b)", 0x4ba00000, 0xffe0003f, 0, 0, I1 },
{"cswr", "t,m(+b)", 0x4bc00000, 0xffe0003f, 0, 0, I1 },
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