PERFORCE change 211546 for review
Robert Watson
rwatson at FreeBSD.org
Tue May 22 20:03:34 UTC 2012
http://p4web.freebsd.org/@@211546?ac=10
Change 211546 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/05/22 20:02:32
Hook up Deimos CP2 utility routine library to CheriBSD, which
requires adapting it a bit for the FreeBSD build environment,
but also fixing some bugs I introduced in CP2 register access
macros when being a bit too agressive trimming NOPs from asm
statements. Allocate a CT0 temporary register.
Affected files ...
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/files.beri#3 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#3 edit
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#4 edit
Differences ...
==== //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/files.beri#3 (text+ko) ====
@@ -14,5 +14,6 @@
dev/terasic/mtl/terasic_mtl_syscons.c optional terasic_mtl
dev/terasic/mtl/terasic_mtl_text.c optional terasic_mtl
mips/beri/beri_machdep.c standard
+mips/cheri/cp2.c optional cpu_cheri
mips/mips/intr_machdep.c standard
mips/mips/tick.c standard
==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#3 (text+ko) ====
@@ -28,8 +28,9 @@
* SUCH DAMAGE.
*/
-#include "include/mips.h"
-#include "include/cp2.h"
+#include <sys/param.h>
+
+#include <mips/cheri/cp2.h>
/*
* Beginnings of a programming interface for explicitly managing capability
@@ -111,26 +112,26 @@
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c0);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c0);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_cv0);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_cv0);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c1);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c1);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_cv1);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_cv1);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c2);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c2);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_ca0);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_ca0);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c3);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c3);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_ca1);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_ca1);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c4);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c4);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_ca2);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_ca2);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c5);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c5);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_ca3);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_ca3);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c6);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c6);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_ct0);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_ct0);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c7);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c7);
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c8);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c8);
@@ -138,6 +139,9 @@
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c9);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c9);
+ CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c10);
+ CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c10);
+
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c11);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c11);
@@ -183,12 +187,6 @@
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_c25);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_c25);
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_rcc);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_rcc);
-
- CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_idc);
- CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_idc);
-
CP2_CR_LOAD(CHERI_CR_CT0, CHERI_CR_KDC, &cf_srcp->cf_tsc);
CP2_CR_STORE(CHERI_CR_CT0, CHERI_CR_KDC, &cf_destp->cf_tsc);
==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.h#4 (text+ko) ====
@@ -72,6 +72,7 @@
* A blend of hardware and software allocation of capability registers.
*/
#define CHERI_CR_C0 0 /* MIPS fetch/load/store capability. */
+#define CHERI_CR_CT0 10 /* CT0: temporary capability. */
#define CHERI_CR_KT0 26 /* KT0: temporary kernel capability. */
#define CHERI_CR_KT1 27 /* KT1: temporary kernel capability. */
#define CHERI_CR_TSC 28 /* TSC: trusted stack capability. */
@@ -132,19 +133,19 @@
*/
#define CP2_CR_GET_BASE(crn, v) do { \
__asm__ __volatile__ ( \
- "cgetbase %0, $c%1; " \
+ "cgetbase %0, $c%1; " : \
"=r" (v) : "i" (crn)); \
} while (0)
#define CP2_CR_GET_UPERMS(crn, v) do { \
__asm__ __volatile__ ( \
- "cgetperms %0, $c%1; " \
+ "cgetperms %0, $c%1; " : \
"=r" (v) : "i" (crn)); \
} while (0)
#define CP2_CR_GET_OTYPE(crn, v) do { \
__asm__ __volatile__ ( \
- "cgettype %0, $c%1; " \
+ "cgettype %0, $c%1; " : \
"=r" (v) : "i" (crn)); \
} while (0)
@@ -152,13 +153,13 @@
#define CP2_CR_GET_LENGTH(crn, v) do { \
__asm__ __volatile__ ( \
- "cgetleng %0, $c%1; " \
+ "cgetleng %0, $c%1; " : \
"=r" (v) : "i" (crn)); \
} while (0)
#define CP2_CR_STORE(crn_from, crn_base, offset) do { \
__asm__ __volatile__ ( \
- "cscr $c%0, $c%1, %2; " \
+ "cscr $c%0, $c%1, %2; " : \
: "i" (crn_from), "i" (crn_base), "r" (offset)); \
} while (0)
@@ -196,60 +197,60 @@
#define CP2_CR_INC_BASE(crn_to, crn_from, v) do { \
if ((crn_to) == 0) \
__asm__ __volatile__ ( \
- "cincbase $c%0, $c%1, %2; " \
+ "cincbase $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v) : \
"memory"); \
else \
__asm__ __volatile__ ( \
- "cincbase $c%0, $c%1, %2; " \
+ "cincbase $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v)); \
} while (0)
#define CP2_CR_AND_UPERMS(crn_to, crn_from, v) do { \
if ((crn_to) == 0) \
__asm__ __volatile__ ( \
- "candperm $c%0, $c%1, %2; " \
+ "candperm $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v) : \
"memory"); \
else \
__asm__ __volatile__ ( \
- "candperm $c%0, $c%1, %2; " \
+ "candperm $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v)); \
} while (0)
#define CP2_CR_SET_OTYPE(crn_to, crn_from, v) do { \
if ((crn_to) == 0) \
__asm__ __volatile__ ( \
- "csettype $c%0, $c%1, %2; " \
+ "csettype $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v) : \
"memory"); \
else \
__asm__ __volatile__ ( \
- "csettype $c%0, $c%1, %2; " \
+ "csettype $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v)); \
} while (0)
#define CP2_CR_SET_LENGTH(crn_to, crn_from, v) do { \
if ((crn_to) == 0) \
__asm__ __volatile__ ( \
- "cdecleng $c%0, $c%1, %2; " \
+ "cdecleng $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v) : \
"memory"); \
else \
__asm__ __volatile__ ( \
- "cdecleng $c%0, $c%1, %2; " \
+ "cdecleng $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_from), "r" (v)); \
} while (0)
#define CP2_CR_LOAD(crn_to, crn_base, offset) do { \
if ((crn_to) == 0) \
__asm__ __volatile__ ( \
- "clcr $c%0, $c%1, %2; " \
+ "clcr $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_base), "r" (offset) : \
"memory"); \
else \
__asm__ __volatile__ ( \
- "clcr $c%0, $c%1, %2; " \
+ "clcr $c%0, $c%1, %2; " : \
: "i" (crn_to), "i" (crn_base), "r" (offset)); \
} while (0)
@@ -287,49 +288,49 @@
*/
#define CP2_LOAD_BYTE_VIA(crn, offset, b) do { \
__asm__ __volatile__ ( \
- "clbr %0, $c%1, %2; " \
+ "clbr %0, $c%1, %2; " : \
"=r" (b) : "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_LOAD_HWORD_VIA(crn, offset, h) do { \
__asm__ __volatile__ ( \
- "clhr %0, $c%1, %2; " \
+ "clhr %0, $c%1, %2; " : \
"=r" (b) : "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_LOAD_WORD_VIA(crn, offset, w) do { \
__asm__ __volatile__ ( \
- "clwr %0, $c%1, %2; " \
+ "clwr %0, $c%1, %2; " : \
"=r" (w) : "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_LOAD_DWORD_VIA(crn, offset, d) do { \
__asm__ __volatile__ ( \
- "cldr %0, $c%1, %2; " \
+ "cldr %0, $c%1, %2; " : \
"=r" (d) : "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_STORE_BYTE_VIA(crn, offset, b) do { \
__asm__ __volatile__ ( \
- "csbr %0, $c%1, %2; " \
+ "csbr %0, $c%1, %2; " : \
: "r" (b), "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_STORE_HWORD_VIA(crn, offset, h) do { \
__asm__ __volatile__ ( \
- "cshr %0, $c%1, %2; " \
+ "cshr %0, $c%1, %2; " : \
: "r" (h), "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_STORE_WORD_VIA(crn, offset, w) do { \
__asm__ __volatile__ ( \
- "cswr %0, $c%1, %2; " \
+ "cswr %0, $c%1, %2; " : \
: "r" (w), "i" (crn), "r" (offset) : "memory"); \
} while (0)
#define CP2_STORE_DWORD_VIA(crn, offset, d) do { \
__asm__ __volatile__ ( \
- "csdr %0, $c%1, %2; " \
+ "csdr %0, $c%1, %2; " : \
: "r" (d), "i" (crn), "r" (offset) : "memory"); \
} while (0)
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