PERFORCE change 211436 for review

[Robert Watson]

http://p4web.freebsd.org/@@211436?ac=10

Change 211436 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/05/20 15:13:52

	Don't try to save $c0 until after CP2 is enabled.

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/locore.S#3 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/locore.S#3 (text+ko) ====

@@ -126,14 +126,6 @@
 #endif
 #endif
 
-#if defined(CPU_CHERI)
-	/*
-	 * On CHERI MIPS, preserve the kernel's data segment context for use
-	 * in exception handlers.  $kcc will be preserved by the first eret.
-	 */
-	cmove	$c30, $c0		# Preserve $kdc
-#endif
-
 	/*
 	 * Read coprocessor 0 status register, clear bits not
 	 * preserved (namely, clearing interrupt bits), and set
@@ -145,6 +137,14 @@
 	mtc0	t2, MIPS_COP_0_STATUS
 	COP0_SYNC
 
+#if defined(CPU_CHERI)
+	/*
+	 * On CHERI MIPS, preserve the kernel's data segment context for use
+	 * in exception handlers.  $kcc will be preserved by the first eret.
+	 */
+	cmove	$c30, $c0		# Preserve $kdc
+#endif
+
 	/* Make sure KSEG0 is cached */
 	li	t0, MIPS_CCA_CACHED
 	mtc0	t0, MIPS_COP_0_CONFIG