PERFORCE change 175767 for review
Rafal Jaworowski
raj at FreeBSD.org
Wed Mar 17 17:41:42 UTC 2010
http://p4web.freebsd.org/chv.cgi?CH=175767
Change 175767 by raj at raj_fdt on 2010/03/17 17:41:20
Clean up legacy #defines a bit.
Affected files ...
.. //depot/projects/fdt/sys/arm/mv/common.c#7 edit
.. //depot/projects/fdt/sys/arm/mv/mvwin.h#3 edit
.. //depot/projects/fdt/sys/arm/mv/orion/orion.c#3 edit
Differences ...
==== //depot/projects/fdt/sys/arm/mv/common.c#7 (text+ko) ====
@@ -336,6 +336,17 @@
/* TODO add info on currently set endianess */
}
+#define MV_USB0_BASE (FDT_IMMR_VA + usb0_base)
+#define MV_CESA_BASE (FDT_IMMR_VA + cesa_base)
+#define MV_ETH0_BASE (FDT_IMMR_VA + eth0_base)
+#define MV_SATAHC_BASE (FDT_IMMR_VA + sata0_base)
+#define MV_XOR_BASE (FDT_IMMR_VA + xor0_base)
+#define MV_IDMA_BASE (FDT_IMMR_VA + idma0_base)
+
+/* XXX these are temporary and should be retrieved from the DT */
+#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320)
+#define MV_ETH1_BASE (MV_ETH0_BASE + 0x4000)
+
int
soc_decode_win(void)
{
@@ -394,25 +405,6 @@
return (0);
}
-/*
- * XXX Redefine macros. This is needed to avoid destroying compatibility with
- * macros to be removed in the future (but currently used elsewhere). This
- * will not be neccessary when fdtbus will be functioning.
- */
-#undef MV_USB0_BASE
-#undef MV_CESA_BASE
-#undef MV_ETH0_BASE
-#undef MV_SATAHC_BASE
-#undef MV_XOR_BASE
-#undef MV_IDMA_BASE
-
-#define MV_USB0_BASE (FDT_IMMR_VA + usb0_base)
-#define MV_CESA_BASE (FDT_IMMR_VA + cesa_base)
-#define MV_ETH0_BASE (FDT_IMMR_VA + eth0_base)
-#define MV_SATAHC_BASE (FDT_IMMR_VA + sata0_base)
-#define MV_XOR_BASE (FDT_IMMR_VA + xor0_base)
-#define MV_IDMA_BASE (FDT_IMMR_VA + idma0_base)
-
/**************************************************************************
* Decode windows registers accessors
**************************************************************************/
==== //depot/projects/fdt/sys/arm/mv/mvwin.h#3 (text+ko) ====
@@ -87,31 +87,14 @@
#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
#define MV_MPP_BASE (MV_BASE + 0x10000)
-#define MV_GPIO_BASE (MV_BASE + 0x10100)
-#define MV_GPIO_SIZE 0x20
-#define MV_RTC_BASE (MV_BASE + 0x10300)
-#define MV_RTC_SIZE 0x08
-#define MV_TWSI0_BASE (MV_BASE + 0x11000)
-#define MV_TWSI1_BASE (MV_BASE + 0x11100)
-#define MV_TWSI_SIZE 0x20
-#define MV_UART0_BASE (MV_BASE + 0x12000)
-#define MV_UART1_BASE (MV_BASE + 0x12100)
-#define MV_UART_SIZE 0x20
+
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
-#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
-#define MV_IC_SIZE 0x3C
-#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300)
-#define MV_TIMERS_SIZE 0x30
+
#define MV_PCI_BASE (MV_BASE + 0x30000)
#define MV_PCI_SIZE 0x2000
-#if defined (SOC_MV_KIRKWOOD)
-#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */
-#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
-#define MV_CESA_BASE (MV_BASE + 0x90000)
-#endif
-#define MV_CESA_SIZE 0x10000
+
#define MV_PCIE_BASE (MV_BASE + 0x40000)
#define MV_PCIE_SIZE 0x2000
@@ -124,27 +107,7 @@
#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
-#define MV_USB0_BASE (MV_BASE + 0x50000)
-#define MV_USB1_BASE (MV_USB0_BASE + 0x1000)
-#define MV_USB2_BASE (MV_USB0_BASE + 0x2000)
-#define MV_USB_SIZE 0x1000
-#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320)
-#define MV_IDMA_BASE (MV_BASE + 0x60000)
-#define MV_IDMA_SIZE 0x1000
-#define MV_XOR_BASE (MV_BASE + 0x60000)
-#define MV_XOR_SIZE 0x1000
-#define MV_ETH0_BASE (MV_BASE + 0x72000)
-#define MV_ETH1_BASE (MV_BASE + 0x76000)
-#define MV_ETH_SIZE 0x2000
-#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD)
-#define MV_SATAHC_BASE (MV_BASE + 0x80000)
-#define MV_SATAHC_SIZE 0x6000
-#elif defined(SOC_MV_DISCOVERY)
-#define MV_SATAHC_BASE (MV_BASE + 0xA0000)
-#define MV_SATAHC_SIZE 0x6000
-#endif
-
-#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
+#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE
/*
* Decode windows definitions and macros
@@ -219,70 +182,70 @@
static __inline uint32_t \
pre ## _ ## reg ## _read(int i) \
{ \
- return (bus_space_read_4(obio_tag, base, off(i))); \
+ return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
}
#define WIN_REG_IDX_RD2(pre,reg,off,base) \
static __inline uint32_t \
pre ## _ ## reg ## _read(int i, int j) \
{ \
- return (bus_space_read_4(obio_tag, base, off(i, j))); \
+ return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
} \
#define WIN_REG_BASE_IDX_RD(pre,reg,off) \
static __inline uint32_t \
pre ## _ ## reg ## _read(uint32_t base, int i) \
{ \
- return (bus_space_read_4(obio_tag, base, off(i))); \
+ return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
}
#define WIN_REG_IDX_WR(pre,reg,off,base) \
static __inline void \
pre ## _ ## reg ## _write(int i, uint32_t val) \
{ \
- bus_space_write_4(obio_tag, base, off(i), val); \
+ bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
}
#define WIN_REG_IDX_WR2(pre,reg,off,base) \
static __inline void \
pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
{ \
- bus_space_write_4(obio_tag, base, off(i, j), val); \
+ bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
}
#define WIN_REG_BASE_IDX_WR(pre,reg,off) \
static __inline void \
pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
{ \
- bus_space_write_4(obio_tag, base, off(i), val); \
+ bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
}
#define WIN_REG_RD(pre,reg,off,base) \
static __inline uint32_t \
pre ## _ ## reg ## _read(void) \
{ \
- return (bus_space_read_4(obio_tag, base, off)); \
+ return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
}
#define WIN_REG_BASE_RD(pre,reg,off) \
static __inline uint32_t \
pre ## _ ## reg ## _read(uint32_t base) \
{ \
- return (bus_space_read_4(obio_tag, base, off)); \
+ return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
}
#define WIN_REG_WR(pre,reg,off,base) \
static __inline void \
pre ## _ ## reg ## _write(uint32_t val) \
{ \
- bus_space_write_4(obio_tag, base, off, val); \
+ bus_space_write_4(fdtbus_bs_tag, base, off, val); \
}
#define WIN_REG_BASE_WR(pre,reg,off) \
static __inline void \
pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
{ \
- bus_space_write_4(obio_tag, base, off, val); \
+ bus_space_write_4(fdtbus_bs_tag, base, off, val); \
}
#endif /* _MVWIN_H_ */
==== //depot/projects/fdt/sys/arm/mv/orion/orion.c#3 (text+ko) ====
@@ -37,6 +37,7 @@
#include <sys/bus.h>
#include <machine/bus.h>
+#include <machine/fdt.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
@@ -112,7 +113,8 @@
* On Orion TCLK is can be configured to 150 MHz or 166 MHz.
* Current setting is read from Sample At Reset register.
*/
- sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET);
+ /* XXX MPP addr should be retrieved from the DT */
+ sar = bus_space_read_4(fdtbus_bs_tag, MV_MPP_BASE, SAMPLE_AT_RESET);
sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
switch (sar) {
case 1:
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