PERFORCE change 175743 for review
Rafal Jaworowski
raj at FreeBSD.org
Tue Mar 16 21:20:15 UTC 2010
http://p4web.freebsd.org/chv.cgi?CH=175743
Change 175743 by raj at raj_fdt on 2010/03/16 21:19:28
Improve and clean up FDT infrastructure on Marvell ARM.
Affected files ...
.. //depot/projects/fdt/sys/arm/mv/common.c#5 edit
.. //depot/projects/fdt/sys/arm/mv/mvwin.h#2 edit
Differences ...
==== //depot/projects/fdt/sys/arm/mv/common.c#5 (text+ko) ====
@@ -41,6 +41,7 @@
#include <dev/ofw/openfirm.h>
#include <machine/bus.h>
+#include <machine/fdt.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
@@ -91,6 +92,8 @@
u_long usb0_base = 0;
u_long eth0_base = 0;
u_long sata0_base = 0;
+u_long idma0_base = 0;
+u_long xor0_base = 0;
static const struct decode_win *cpu_wins = cpu_win_tbl;
@@ -104,6 +107,8 @@
{ "mrvl,ge", ð0_base },
{ "mrvl,usb-ehci", &usb0_base },
{ "mrvl,sata", &sata0_base },
+ { "mrvl,xor", &xor0_base},
+ { "mrvl,idma", &idma0_base},
{ NULL, NULL },
};
@@ -186,14 +191,14 @@
read_cpu_ctrl(uint32_t reg)
{
- return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
+ return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
}
void
write_cpu_ctrl(uint32_t reg, uint32_t val)
{
- bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val);
+ bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
}
void
@@ -265,8 +270,8 @@
* possible) after the internal registers range has been mapped in via
* pmap_devmap_bootstrap().
*/
- *dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16;
- *rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff;
+ *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
+ *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
}
void
@@ -396,11 +401,15 @@
#undef MV_CESA_BASE
#undef MV_ETH0_BASE
#undef MV_SATAHC_BASE
+#undef MV_XOR_BASE
+#undef MV_IDMA_BASE
-#define MV_USB0_BASE (MV_BASE + usb0_base)
-#define MV_CESA_BASE (MV_BASE + cesa_base)
-#define MV_ETH0_BASE (MV_BASE + eth0_base)
-#define MV_SATAHC_BASE (MV_BASE + sata0_base)
+#define MV_USB0_BASE (FDT_IMMR_VA + usb0_base)
+#define MV_CESA_BASE (FDT_IMMR_VA + cesa_base)
+#define MV_ETH0_BASE (FDT_IMMR_VA + eth0_base)
+#define MV_SATAHC_BASE (FDT_IMMR_VA + sata0_base)
+#define MV_XOR_BASE (FDT_IMMR_VA + xor0_base)
+#define MV_IDMA_BASE (FDT_IMMR_VA + idma0_base)
/**************************************************************************
* Decode windows registers accessors
@@ -496,7 +505,7 @@
printf("\n");
}
printf("Internal regs base: 0x%08x\n",
- bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
+ bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
for (i = 0; i < MV_WIN_DDR_MAX; i++)
printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
@@ -1784,11 +1793,8 @@
if (fdt_get_regsize(node, &sram_base, &sram_size) != 0)
return (EINVAL);
- /*
- * XXX Need to handle different CESA SRAM target ID accross SOCs.
- */
- cpu_win_tbl[++t].target = 4;
- cpu_win_tbl[t].attr = 0;
+ cpu_win_tbl[++t].target = MV_WIN_CESA_TARGET;
+ cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR;
cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;
cpu_win_tbl[t].remap = -1;
==== //depot/projects/fdt/sys/arm/mv/mvwin.h#2 (text+ko) ====
@@ -167,6 +167,14 @@
#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00)
#define MV_WIN_CESA_MAX 4
+#if defined(SOC_MV_DISCOVERY)
+#define MV_WIN_CESA_TARGET 9
+#define MV_WIN_CESA_ATTR 1
+#else
+#define MV_WIN_CESA_TARGET 3
+#define MV_WIN_CESA_ATTR 0
+#endif
+
#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0)
#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4)
#define MV_WIN_USB_MAX 4
More information about the p4-projects
mailing list