PERFORCE change 163745 for review
Alexander Motin
mav at FreeBSD.org
Sun Jun 7 22:39:18 UTC 2009
http://perforce.freebsd.org/chv.cgi?CH=163745
Change 163745 by mav at mav_mavbook on 2009/06/07 22:38:27
Massive cleaning.
Affected files ...
.. //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.c#18 edit
.. //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.h#6 edit
Differences ...
==== //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.c#18 (text+ko) ====
@@ -82,8 +82,8 @@
static void ahci_start_fr(device_t dev);
static void ahci_stop_fr(device_t dev);
-static int ata_sata_connect(struct ahci_channel *ch);
-static int ata_sata_phy_reset(device_t dev, int quick);
+static int ahci_sata_connect(struct ahci_channel *ch);
+static int ahci_sata_phy_reset(device_t dev, int quick);
static void ahciaction(struct cam_sim *sim, union ccb *ccb);
static void ahcipoll(struct cam_sim *sim);
@@ -470,17 +470,6 @@
ahci_dmainit(dev);
ahci_slotsalloc(dev);
-
- /* set the SATA resources */
- ch->r_io[ATA_SSTATUS].res = ch->r_mem;
- ch->r_io[ATA_SSTATUS].offset = AHCI_P_SSTS;
- ch->r_io[ATA_SERROR].res = ch->r_mem;
- ch->r_io[ATA_SERROR].offset = AHCI_P_SERR;
- ch->r_io[ATA_SCONTROL].res = ch->r_mem;
- ch->r_io[ATA_SCONTROL].offset = AHCI_P_SCTL;
- ch->r_io[ATA_SACTIVE].res = ch->r_mem;
- ch->r_io[ATA_SACTIVE].offset = AHCI_P_SACT;
-
ahci_ch_resume(dev);
mtx_lock(&ch->mtx);
@@ -578,12 +567,12 @@
ahci_stop_fr(dev);
ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
/* Allow everything, including partial and slumber modes. */
- ATA_IDX_OUTL(ch, ATA_SCONTROL, 0);
+ ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
/* Request slumber mode transition and give some time to get there. */
ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
DELAY(100);
/* Disable PHY. */
- ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE);
+ ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
return (0);
}
@@ -612,7 +601,6 @@
return (0);
}
-
devclass_t ahcich_devclass;
static device_method_t ahcich_methods[] = {
DEVMETHOD(device_probe, ahci_ch_probe),
@@ -629,17 +617,172 @@
};
DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0);
+struct ahci_dc_cb_args {
+ bus_addr_t maddr;
+ int error;
+};
+
+static void
+ahci_dmainit(device_t dev)
+{
+ struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
+ struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_dc_cb_args dcba;
+
+ ch->dma.alignment = 2;
+ ch->dma.boundary = 65536;
+ ch->dma.segsize = 65536;
+ ch->dma.max_iosize = AHCI_DMA_ENTRIES * PAGE_SIZE;
+ if (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_64BIT)
+ ch->dma.max_address = BUS_SPACE_MAXADDR;
+ else
+ ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
+
+ if (bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 64 * 1024,
+ ch->dma.max_address, BUS_SPACE_MAXADDR,
+ NULL, NULL, MAXWSPCSZ, 1, MAXWSPCSZ,
+ 0, NULL, NULL, &ch->dma.work_tag))
+ goto error;
+
+ if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
+ &ch->dma.work_map))
+ goto error;
+
+ if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
+ MAXWSPCSZ, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
+ bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
+ goto error;
+ }
+ ch->dma.work_bus = dcba.maddr;
+
+ if (bus_dma_tag_create(bus_get_dma_tag(dev),
+ ch->dma.alignment, ch->dma.boundary,
+ ch->dma.max_address, BUS_SPACE_MAXADDR,
+ NULL, NULL,
+ ch->dma.max_iosize * AHCI_MAX_SLOTS,
+ AHCI_DMA_ENTRIES, ch->dma.segsize,
+ 0, NULL, NULL, &ch->dma.data_tag)) {
+ goto error;
+ }
+ return;
+
+error:
+ device_printf(dev, "WARNING - DMA initialization failed, disabling DMA\n");
+ ahci_dmafini(dev);
+}
+
+static void
+ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
+{
+ struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
+
+ if (!(dcba->error = error))
+ dcba->maddr = segs[0].ds_addr;
+}
+
+static void
+ahci_dmafini(device_t dev)
+{
+ struct ahci_channel *ch = device_get_softc(dev);
+
+ if (ch->dma.data_tag) {
+ bus_dma_tag_destroy(ch->dma.data_tag);
+ ch->dma.data_tag = NULL;
+ }
+ if (ch->dma.work_bus) {
+ bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
+ bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
+ ch->dma.work_bus = 0;
+ ch->dma.work_map = NULL;
+ ch->dma.work = NULL;
+ }
+ if (ch->dma.work_tag) {
+ bus_dma_tag_destroy(ch->dma.work_tag);
+ ch->dma.work_tag = NULL;
+ }
+}
+
static void
+ahci_slotsalloc(device_t dev)
+{
+ struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_dc_cb_args dcba;
+ int i;
+
+ /* Alloc and setup command/dma slots */
+ bzero(ch->slot, sizeof(ch->slot));
+ for (i = 0; i < AHCI_MAX_SLOTS; i++) {
+ struct ahci_slot *slot = &ch->slot[i];
+
+ slot->dev = dev;
+ slot->slot = i;
+ slot->state = AHCI_SLOT_EMPTY;
+ slot->ccb = NULL;
+ callout_init_mtx(&slot->timeout, &ch->mtx, 0);
+
+ if (bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, PAGE_SIZE,
+ ch->dma.max_address, BUS_SPACE_MAXADDR,
+ NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE,
+ 0, NULL, NULL, &slot->dma.sg_tag)) {
+ device_printf(ch->dev, "FAILURE - create sg_tag\n");
+ }
+
+ if (bus_dmamem_alloc(slot->dma.sg_tag, (void **)&slot->dma.sg,
+ 0, &slot->dma.sg_map))
+ device_printf(ch->dev, "FAILURE - alloc sg_map\n");
+
+ if (bus_dmamap_load(slot->dma.sg_tag, slot->dma.sg_map, slot->dma.sg, PAGE_SIZE,
+ ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT) || dcba.error)
+ device_printf(ch->dev, "FAILURE - load sg\n");
+ slot->dma.sg_bus = dcba.maddr;
+
+ if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
+ device_printf(ch->dev, "FAILURE - create data_map\n");
+ }
+}
+
+static void
+ahci_slotsfree(device_t dev)
+{
+ struct ahci_channel *ch = device_get_softc(dev);
+ int i;
+
+ /* Free all dma slots */
+ for (i = 0; i < AHCI_MAX_SLOTS; i++) {
+ struct ahci_slot *slot = &ch->slot[i];
+
+ if (slot->dma.sg_tag) {
+ bus_dma_tag_destroy(slot->dma.sg_tag);
+ slot->dma.sg_tag = NULL;
+ }
+ if (slot->dma.sg_bus) {
+ bus_dmamap_unload(slot->dma.sg_tag, slot->dma.sg_map);
+ slot->dma.sg_bus = 0;
+ }
+ if (slot->dma.sg_map) {
+ bus_dmamem_free(slot->dma.sg_tag, slot->dma.sg, slot->dma.sg_map);
+ bus_dmamap_destroy(slot->dma.sg_tag, slot->dma.sg_map);
+ slot->dma.sg = NULL;
+ slot->dma.sg_map = NULL;
+ }
+ if (slot->dma.data_map) {
+ bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
+ slot->dma.data_map = NULL;
+ }
+ }
+}
+
+static void
ahci_phy_check_events(device_t dev)
{
struct ahci_channel *ch = device_get_softc(dev);
- u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
+ u_int32_t error = ATA_INL(ch->r_mem, AHCI_P_SERR);
/* Clear error bits/interrupt */
- ATA_IDX_OUTL(ch, ATA_SERROR, error);
+ ATA_OUTL(ch->r_mem, AHCI_P_SERR, error);
/* If we have a connection event deal with it */
if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
- u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
+ u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
@@ -667,7 +810,7 @@
/* Read interrupt and command statuses. */
istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
cstatus = ATA_INL(ch->r_mem, AHCI_P_CI);
- sstatus = ATA_IDX_INL(ch, ATA_SACTIVE);
+ sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
//device_printf(dev, "%s is %08x cs %08x ss %08x rslots %08x\n", __func__, istatus, cstatus, sstatus, ch->rslots);
/* Clear interrupt(s) */
@@ -724,7 +867,7 @@
struct ahci_slot *slot;
int tag;
- tag = ch->lastslot;
+ tag = ch->lastslot;
do {
tag++;
if (tag >= AHCI_MAX_SLOTS)
@@ -843,7 +986,7 @@
if ((slot->ccb->ccb_h.func_code == XPT_ATA_IO) &&
(slot->ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
ch->aslots |= (1 << slot->slot);
- ATA_IDX_OUTL(ch, ATA_SACTIVE, 1 << slot->slot);
+ ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
}
/* Issue command to the controller. */
slot->state = AHCI_SLOT_RUNNING;
@@ -854,14 +997,14 @@
ATA_INL(ch->r_mem, AHCI_P_CI),
ATA_INL(ch->r_mem, AHCI_P_IS),
ATA_INL(ch->r_mem, AHCI_P_TFD),
- ATA_IDX_INL(ch, ATA_SERROR),
+ ATA_INL(ch->r_mem, AHCI_P_SERR),
ATA_INL(ch->r_mem, AHCI_P_SIG));
DELAY(100000);
printf("ci %08x is %08x tfd %08x serr %08x sign %08x\n",
ATA_INL(ch->r_mem, AHCI_P_CI),
ATA_INL(ch->r_mem, AHCI_P_IS),
ATA_INL(ch->r_mem, AHCI_P_TFD),
- ATA_IDX_INL(ch, ATA_SERROR),
+ ATA_INL(ch->r_mem, AHCI_P_SERR),
ATA_INL(ch->r_mem, AHCI_P_SIG));
*/
/* Device reset commands doesn't interrupt. Poll them. */
@@ -1002,7 +1145,7 @@
u_int32_t cmd;
/* Clear SATA error register */
- ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
+ ATA_OUTL(ch->r_mem, AHCI_P_SERR, ATA_INL(ch->r_mem, AHCI_P_SERR));
/* Clear any interrupts pending on this channel */
ATA_OUTL(ch->r_mem, AHCI_P_IS, ATA_INL(ch->r_mem, AHCI_P_IS));
/* Start operations on this channel */
@@ -1120,7 +1263,7 @@
*signature = 0xffffffff;
ahci_stop(dev);
/* Reset port */
- if (!ata_sata_phy_reset(dev, 0))
+ if (!ahci_sata_phy_reset(dev, 0))
return (ENOENT);
/* Wait for clearing busy status. */
if (ahci_wait_ready(dev, 10000)) {
@@ -1170,176 +1313,6 @@
xpt_async(AC_BUS_RESET, ch->path, NULL);
}
-struct ahci_dc_cb_args {
- bus_addr_t maddr;
- int error;
-};
-
-static void
-ahci_dmainit(device_t dev)
-{
- struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ahci_channel *ch = device_get_softc(dev);
- struct ahci_dc_cb_args dcba;
-
- /* note start and stop are not used here */
- ch->dma.max_iosize = 8192 * DEV_BSIZE;
- if (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_64BIT)
- ch->dma.max_address = BUS_SPACE_MAXADDR;
-
- ch->dma.alignment = 2;
- ch->dma.boundary = 65536;
- ch->dma.segsize = 65536;
- ch->dma.max_iosize = 128 * DEV_BSIZE;
- ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
-
- if (bus_dma_tag_create(bus_get_dma_tag(dev), ch->dma.alignment, 0,
- ch->dma.max_address, BUS_SPACE_MAXADDR,
- NULL, NULL, ch->dma.max_iosize,
- ATA_DMA_ENTRIES, ch->dma.segsize,
- 0, NULL, NULL, &ch->dma.dmatag))
- goto error;
-
- if (bus_dma_tag_create(ch->dma.dmatag, PAGE_SIZE, 64 * 1024,
- ch->dma.max_address, BUS_SPACE_MAXADDR,
- NULL, NULL, MAXWSPCSZ, 1, MAXWSPCSZ,
- 0, NULL, NULL, &ch->dma.work_tag))
- goto error;
-
- if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
- &ch->dma.work_map))
- goto error;
-
- if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
- MAXWSPCSZ, ahci_dmasetupc_cb, &dcba, 0) ||
- dcba.error) {
- bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
- goto error;
- }
- ch->dma.work_bus = dcba.maddr;
-
- if (bus_dma_tag_create(ch->dma.dmatag,
- ch->dma.alignment, ch->dma.boundary,
- ch->dma.max_address, BUS_SPACE_MAXADDR,
- NULL, NULL,
- ch->dma.max_iosize * AHCI_MAX_SLOTS,
- ATA_DMA_ENTRIES, ch->dma.segsize,
- 0, NULL, NULL, &ch->dma.data_tag)) {
- goto error;
- }
-
- return;
-
-error:
- device_printf(dev, "WARNING - DMA initialization failed, disabling DMA\n");
- ahci_dmafini(dev);
-}
-
-static void
-ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
-{
- struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
-
- if (!(dcba->error = error))
- dcba->maddr = segs[0].ds_addr;
-}
-
-static void
-ahci_dmafini(device_t dev)
-{
- struct ahci_channel *ch = device_get_softc(dev);
-
- if (ch->dma.data_tag) {
- bus_dma_tag_destroy(ch->dma.data_tag);
- ch->dma.data_tag = NULL;
- }
- if (ch->dma.work_bus) {
- bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
- bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
- ch->dma.work_bus = 0;
- ch->dma.work_map = NULL;
- ch->dma.work = NULL;
- }
- if (ch->dma.work_tag) {
- bus_dma_tag_destroy(ch->dma.work_tag);
- ch->dma.work_tag = NULL;
- }
- if (ch->dma.dmatag) {
- bus_dma_tag_destroy(ch->dma.dmatag);
- ch->dma.dmatag = NULL;
- }
-}
-
-static void
-ahci_slotsalloc(device_t dev)
-{
- struct ahci_channel *ch = device_get_softc(dev);
- struct ahci_dc_cb_args dcba;
- int i;
-
- /* Alloc and setup command/dma slots */
- bzero(ch->slot, sizeof(ch->slot));
- for (i = 0; i < AHCI_MAX_SLOTS; i++) {
- struct ahci_slot *slot = &ch->slot[i];
-
- slot->dev = dev;
- slot->slot = i;
- slot->state = AHCI_SLOT_EMPTY;
- slot->ccb = NULL;
- callout_init_mtx(&slot->timeout, &ch->mtx, 0);
-
- if (bus_dma_tag_create(ch->dma.dmatag, PAGE_SIZE, PAGE_SIZE,
- ch->dma.max_address, BUS_SPACE_MAXADDR,
- NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE,
- 0, NULL, NULL, &slot->dma.sg_tag)) {
- device_printf(ch->dev, "FAILURE - create sg_tag\n");
- }
-
- if (bus_dmamem_alloc(slot->dma.sg_tag, (void **)&slot->dma.sg,
- 0, &slot->dma.sg_map))
- device_printf(ch->dev, "FAILURE - alloc sg_map\n");
-
- if (bus_dmamap_load(slot->dma.sg_tag, slot->dma.sg_map, slot->dma.sg, PAGE_SIZE,
- ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT) || dcba.error)
- device_printf(ch->dev, "FAILURE - load sg\n");
- slot->dma.sg_bus = dcba.maddr;
-
- if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
- device_printf(ch->dev, "FAILURE - create data_map\n");
- }
-}
-
-static void
-ahci_slotsfree(device_t dev)
-{
- struct ahci_channel *ch = device_get_softc(dev);
- int i;
-
- /* Free all dma slots */
- for (i = 0; i < AHCI_MAX_SLOTS; i++) {
- struct ahci_slot *slot = &ch->slot[i];
-
- if (slot->dma.sg_tag) {
- bus_dma_tag_destroy(slot->dma.sg_tag);
- slot->dma.sg_tag = NULL;
- }
- if (slot->dma.sg_bus) {
- bus_dmamap_unload(slot->dma.sg_tag, slot->dma.sg_map);
- slot->dma.sg_bus = 0;
- }
- if (slot->dma.sg_map) {
- bus_dmamem_free(slot->dma.sg_tag, slot->dma.sg, slot->dma.sg_map);
- bus_dmamap_destroy(slot->dma.sg_tag, slot->dma.sg_map);
- slot->dma.sg = NULL;
- slot->dma.sg_map = NULL;
- }
- if (slot->dma.data_map) {
- bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
- slot->dma.data_map = NULL;
- }
- }
-}
-
static int
ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
{
@@ -1390,14 +1363,14 @@
}
static int
-ata_sata_connect(struct ahci_channel *ch)
+ahci_sata_connect(struct ahci_channel *ch)
{
u_int32_t status;
int timeout;
/* Wait up to 1 second for "connect well" */
for (timeout = 0; timeout < 1000 ; timeout++) {
- status = ATA_IDX_INL(ch, ATA_SSTATUS);
+ status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
@@ -1416,30 +1389,30 @@
timeout, status);
}
/* Clear SATA error register */
- ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
+ ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
return (1);
}
static int
-ata_sata_phy_reset(device_t dev, int quick)
+ahci_sata_phy_reset(device_t dev, int quick)
{
struct ahci_channel *ch = device_get_softc(dev);
uint32_t val;
if (quick) {
- val = ATA_IDX_INL(ch, ATA_SCONTROL);
+ val = ATA_INL(ch->r_mem, AHCI_P_SCTL);
if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
- return (ata_sata_connect(ch));
+ return (ahci_sata_connect(ch));
}
if (bootverbose)
device_printf(dev, "hardware reset ...\n");
- ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
+ ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_RESET);
DELAY(50000);
- ATA_IDX_OUTL(ch, ATA_SCONTROL,
+ ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
ATA_SC_DET_IDLE /*| ATA_SC_SPD_SPEED_GEN1*/ | ((ch->pm_level > 0) ? 0 :
ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
- return (ata_sata_connect(ch));
+ return (ahci_sata_connect(ch));
}
static void
@@ -1490,9 +1463,9 @@
cts->proto_specific.valid = 0;
cts->xport_specific.sata.valid = CTS_SATA_VALID_SPEED;
if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
- status = ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_SPD_MASK;
+ status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
else
- status = ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_SPD_MASK;
+ status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SC_SPD_MASK;
if (status & ATA_SS_SPD_GEN3)
cts->xport_specific.sata.bitrate = 600000;
else if (status & ATA_SS_SPD_GEN2)
==== //depot/projects/scottl-camlock/src/sys/dev/ahci/ahci.h#6 (text+ko) ====
@@ -76,10 +76,6 @@
#define ATA_S_BUSY 0x80 /* busy */
#define ATA_CONTROL 12 /* (W) control */
-
-#define ATA_CTLOFFSET 0x206 /* control register offset */
-#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
-#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
#define ATA_A_IDS 0x02 /* disable interrupts */
#define ATA_A_RESET 0x04 /* RESET controller */
#define ATA_A_4BIT 0x08 /* 4 head bits */
@@ -105,13 +101,6 @@
#define ATA_SS_IPM_PARTIAL 0x00000200
#define ATA_SS_IPM_SLUMBER 0x00000600
-#define ATA_SS_CONWELL_MASK \
- (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
-#define ATA_SS_CONWELL_GEN1 \
- (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
-#define ATA_SS_CONWELL_GEN2 \
- (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
-
#define ATA_SERROR 14
#define ATA_SE_DATA_CORRECTED 0x00000001
#define ATA_SE_COMM_CORRECTED 0x00000002
@@ -286,63 +275,12 @@
u_int64_t cmd_table_phys; /* 128byte aligned */
} __packed;
-
/* DMA register defines */
#define ATA_DMA_ENTRIES 256
-#define ATA_DMA_EOT 0x80000000
-
-#define ATA_BMCMD_PORT 17
-#define ATA_BMCMD_START_STOP 0x01
-#define ATA_BMCMD_WRITE_READ 0x08
-
-#define ATA_BMDEVSPEC_0 18
-#define ATA_BMSTAT_PORT 19
-#define ATA_BMSTAT_ACTIVE 0x01
-#define ATA_BMSTAT_ERROR 0x02
-#define ATA_BMSTAT_INTERRUPT 0x04
-#define ATA_BMSTAT_MASK 0x07
-#define ATA_BMSTAT_DMA_MASTER 0x20
-#define ATA_BMSTAT_DMA_SLAVE 0x40
-#define ATA_BMSTAT_DMA_SIMPLEX 0x80
-
-#define ATA_BMDEVSPEC_1 20
-#define ATA_BMDTP_PORT 21
-#define ATA_IDX_ADDR 22
-#define ATA_IDX_DATA 23
-#define ATA_MAX_RES 24
-
/* misc defines */
-#define ATA_PRIMARY 0x1f0
-#define ATA_SECONDARY 0x170
-#define ATA_PC98_BANK 0x432
-#define ATA_IOSIZE 0x08
-#define ATA_PC98_IOSIZE 0x10
-#define ATA_CTLIOSIZE 0x01
-#define ATA_BMIOSIZE 0x08
-#define ATA_PC98_BANKIOSIZE 0x01
-#define ATA_IOADDR_RID 0
-#define ATA_CTLADDR_RID 1
-#define ATA_BMADDR_RID 0x20
-#define ATA_PC98_CTLADDR_RID 8
-#define ATA_PC98_BANKADDR_RID 9
#define ATA_IRQ_RID 0
-#define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0)
-#define ATA_CFA_MAGIC1 0x844A
-#define ATA_CFA_MAGIC2 0x848A
-#define ATA_CFA_MAGIC3 0x8400
-#define ATAPI_MAGIC_LSB 0x14
-#define ATAPI_MAGIC_MSB 0xeb
-#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
-#define ATAPI_P_WRITE (ATA_S_DRQ)
-#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
-#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
-#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
-#define ATAPI_P_ABORT 0
#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
-#define ATA_OP_CONTINUES 0
-#define ATA_OP_FINISHED 1
-#define ATA_MAX_28BIT_LBA 268435455UL
/* structure for holding DMA Physical Region Descriptors (PRD) entries */
struct ata_dma_prdentry {
@@ -385,12 +323,6 @@
#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */
};
-/* structure holding resources for an ATA channel */
-struct ata_resource {
- struct resource *res;
- int offset;
-};
-
#define ATA_MASTER 0x00
#define ATA_SLAVE 0x01
#define ATA_PM 0x0f
@@ -419,7 +351,6 @@
struct ahci_channel {
device_t dev; /* device handle */
int unit; /* physical channel */
- struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
struct resource *r_mem;
struct resource *r_irq; /* interrupt of this channel */
void *ih; /* interrupt handle */
@@ -475,13 +406,6 @@
AHCI_ERR_TIMEOUT
};
-/* disk bay/enclosure related */
-#define ATA_LED_OFF 0x00
-#define ATA_LED_RED 0x01
-#define ATA_LED_GREEN 0x02
-#define ATA_LED_ORANGE 0x03
-#define ATA_LED_MASK 0x03
-
/* macros to hide busspace uglyness */
#define ATA_INB(res, offset) \
bus_read_1((res), (offset))
@@ -511,45 +435,3 @@
bus_write_multi_4((res), (offset), (addr), (count))
#define ATA_OUTSL_STRM(res, offset, addr, count) \
bus_write_multi_stream_4((res), (offset), (addr), (count))
-
-#define ATA_IDX_INB(ch, idx) \
- ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
-
-#define ATA_IDX_INW(ch, idx) \
- ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
-
-#define ATA_IDX_INL(ch, idx) \
- ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
-
-#define ATA_IDX_INSW(ch, idx, addr, count) \
- ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
- ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_INSL(ch, idx, addr, count) \
- ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
- ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_OUTB(ch, idx, value) \
- ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
-
-#define ATA_IDX_OUTW(ch, idx, value) \
- ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
-
-#define ATA_IDX_OUTL(ch, idx, value) \
- ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
-
-#define ATA_IDX_OUTSW(ch, idx, addr, count) \
- ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
- ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_OUTSL(ch, idx, addr, count) \
- ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
-
-#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
- ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
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