PERFORCE change 149465 for review
Rafal Jaworowski
raj at FreeBSD.org
Tue Sep 9 09:49:13 UTC 2008
http://perforce.freebsd.org/chv.cgi?CH=149465
Change 149465 by raj at raj_mimi on 2008/09/09 09:48:21
Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are integrated on 88F6281 (Kirkwood) and MV78100 (Discovery)
SOC families.
This includes L2 cache operation routines for the unified L2 cache subsystem
found along with the CPU core in some of them.
Obtained from: Marvell, Semihalf
Affected files ...
.. //depot/projects/arm/src/sys/arm/arm/cpufunc.c#20 edit
.. //depot/projects/arm/src/sys/arm/arm/cpufunc_asm_feroceon.S#1 add
.. //depot/projects/arm/src/sys/arm/arm/identcpu.c#16 edit
.. //depot/projects/arm/src/sys/arm/include/armreg.h#8 edit
.. //depot/projects/arm/src/sys/arm/include/cpufunc.h#11 edit
.. //depot/projects/arm/src/sys/arm/mv/files.mv#4 edit
Differences ...
==== //depot/projects/arm/src/sys/arm/arm/cpufunc.c#20 (text+ko) ====
@@ -357,6 +357,66 @@
arm10_setup /* cpu setup */
};
+
+struct cpu_functions feroceon_cpufuncs = {
+ /* CPU functions */
+
+ cpufunc_id, /* id */
+ cpufunc_nullop, /* cpwait */
+
+ /* MMU functions */
+
+ cpufunc_control, /* control */
+ cpufunc_domains, /* Domain */
+ feroceon_setttb, /* Setttb */
+ cpufunc_faultstatus, /* Faultstatus */
+ cpufunc_faultaddress, /* Faultaddress */
+
+ /* TLB functions */
+
+ armv4_tlb_flushID, /* tlb_flushID */
+ arm10_tlb_flushID_SE, /* tlb_flushID_SE */
+ armv4_tlb_flushI, /* tlb_flushI */
+ arm10_tlb_flushI_SE, /* tlb_flushI_SE */
+ armv4_tlb_flushD, /* tlb_flushD */
+ armv4_tlb_flushD_SE, /* tlb_flushD_SE */
+
+ /* Cache operations */
+
+ armv5_ec_icache_sync_all, /* icache_sync_all */
+ armv5_ec_icache_sync_range, /* icache_sync_range */
+
+ armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */
+ feroceon_dcache_wbinv_range, /* dcache_wbinv_range */
+ feroceon_dcache_inv_range, /* dcache_inv_range */
+ feroceon_dcache_wb_range, /* dcache_wb_range */
+
+ armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */
+ feroceon_idcache_wbinv_range, /* idcache_wbinv_all */
+
+ feroceon_l2cache_wbinv_all, /* l2cache_wbinv_all */
+ feroceon_l2cache_wbinv_range, /* l2cache_wbinv_range */
+ feroceon_l2cache_inv_range, /* l2cache_inv_range */
+ feroceon_l2cache_wb_range, /* l2cache_wb_range */
+
+ /* Other functions */
+
+ cpufunc_nullop, /* flush_prefetchbuf */
+ armv4_drain_writebuf, /* drain_writebuf */
+ cpufunc_nullop, /* flush_brnchtgt_C */
+ (void *)cpufunc_nullop, /* flush_brnchtgt_E */
+
+ (void *)cpufunc_nullop, /* sleep */
+
+ /* Soft functions */
+
+ cpufunc_null_fixup, /* dataabt_fixup */
+ cpufunc_null_fixup, /* prefetchabt_fixup */
+
+ arm10_context_switch, /* context_switch */
+
+ arm10_setup /* cpu setup */
+};
#endif /* CPU_ARM9E || CPU_ARM10 */
#ifdef CPU_ARM10
@@ -933,9 +993,36 @@
}
#endif /* CPU_ARM9 */
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
- if (cputype == CPU_ID_ARM926EJS ||
- cputype == CPU_ID_ARM1026EJS) {
- cpufuncs = armv5_ec_cpufuncs;
+ if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS ||
+ cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD ||
+ cputype == CPU_ID_MV88FR571_41) {
+ if (cputype == CPU_ID_MV88FR131 ||
+ cputype == CPU_ID_MV88FR571_VD ||
+ cputype == CPU_ID_MV88FR571_41) {
+
+ cpufuncs = feroceon_cpufuncs;
+ /*
+ * Workaround for Marvell MV78100 CPU: Cache prefetch
+ * mechanism may affect the cache coherency validity,
+ * so it needs to be disabled.
+ *
+ * Refer to errata document MV-S501058-00C.pdf (p. 3.1
+ * L2 Prefetching Mechanism) for details.
+ */
+ if (cputype == CPU_ID_MV88FR571_VD ||
+ cputype == CPU_ID_MV88FR571_41) {
+ feroceon_control_ext(0xffffffff,
+ FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
+ FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN |
+ FC_L2_PREF_DIS);
+ } else {
+ feroceon_control_ext(0xffffffff,
+ FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
+ FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN);
+ }
+ } else
+ cpufuncs = armv5_ec_cpufuncs;
+
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
pmap_pte_init_generic();
==== //depot/projects/arm/src/sys/arm/arm/identcpu.c#16 (text+ko) ====
@@ -75,7 +75,8 @@
CPU_CLASS_ARM10EJ,
CPU_CLASS_SA1,
CPU_CLASS_XSCALE,
- CPU_CLASS_ARM11J
+ CPU_CLASS_ARM11J,
+ CPU_CLASS_MARVELL
};
static const char * const generic_steppings[16] = {
@@ -304,6 +305,15 @@
{ CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
generic_steppings },
+ { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131",
+ generic_steppings },
+
+ { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD",
+ generic_steppings },
+
+ { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571",
+ generic_steppings },
+
{ 0, CPU_CLASS_NONE, NULL, NULL }
};
==== //depot/projects/arm/src/sys/arm/include/armreg.h#8 (text+ko) ====
@@ -148,6 +148,9 @@
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
+#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
+#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
+#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
#define CPU_ID_FA526 0x66015260
#define CPU_ID_SA1110 0x6901b110
#define CPU_ID_IXP1200 0x6901c120
@@ -253,6 +256,18 @@
/* Xscale Core 3 only */
#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */
+/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
+#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
+#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
+#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */
+#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */
+#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
+#define FC_L2CACHE_EN 0x00400000 /* L2 enable */
+#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */
+#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */
+#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */
+#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */
+
/* Cache type register definitions */
#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
==== //depot/projects/arm/src/sys/arm/include/cpufunc.h#11 (text+ko) ====
@@ -376,6 +376,18 @@
extern unsigned arm10_dcache_sets_inc;
extern unsigned arm10_dcache_index_max;
extern unsigned arm10_dcache_index_inc;
+
+u_int feroceon_control_ext (u_int, u_int);
+void feroceon_setttb (u_int);
+void feroceon_dcache_wbinv_range (vm_offset_t, vm_size_t);
+void feroceon_dcache_inv_range (vm_offset_t, vm_size_t);
+void feroceon_dcache_wb_range (vm_offset_t, vm_size_t);
+void feroceon_idcache_wbinv_range (vm_offset_t, vm_size_t);
+
+void feroceon_l2cache_wbinv_range (vm_offset_t, vm_size_t);
+void feroceon_l2cache_inv_range (vm_offset_t, vm_size_t);
+void feroceon_l2cache_wb_range (vm_offset_t, vm_size_t);
+void feroceon_l2cache_wbinv_all (void);
#endif
#ifdef CPU_ARM11
==== //depot/projects/arm/src/sys/arm/mv/files.mv#4 (text+ko) ====
@@ -15,6 +15,7 @@
arm/arm/bus_space_generic.c standard
arm/arm/cpufunc_asm_arm10.S standard
arm/arm/cpufunc_asm_armv5_ec.S standard
+arm/arm/cpufunc_asm_feroceon.S standard
arm/arm/irq_dispatch.S standard
arm/mv/bus_space.c standard
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