PERFORCE change 136737 for review

Juli Mallett juli at clockworksquid.com
Mon Mar 3 18:16:11 UTC 2008


* "M. Warner Losh" <imp at bsdimp.com> [ 2008-03-03 ]
	[ Re: PERFORCE change 136737 for review ]
> In message: <200803031313.m23DDJv0034582 at repoman.freebsd.org>
>             "Randall R. Stewart" <rrs at FreeBSD.org> writes:
> : http://perforce.freebsd.org/chv.cgi?CH=136737
> : 
> : Change 136737 by rrs at rrs-mips2-jnpr on 2008/03/03 13:13:06
> : 
> : 	Found real source of PG_G problem, the proper intial
> : 	       value for a CACHED page is PG_CACHE not PG_CACHED. 
> : 	       PG_CACHED is defined in vm to be 1, where as PG_CACHE
> : 	       is 0x18 (the proper value for us and defined in pte.h).
> : 
> : Affected files ...
> : 
> : .. //depot/projects/mips2-jnpr/src/sys/mips/include/pte.h#5 edit
> : 
> : Differences ...
> : 
> : ==== //depot/projects/mips2-jnpr/src/sys/mips/include/pte.h#5 (text+ko) ====
> : 
> : @@ -110,8 +110,8 @@
> :  #define	PG_UNCACHED	0x00000010
> :  #define	PG_CACHE	0x00000018
> :  #define	PG_CACHEMODE	0x00000038
> : -#define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
> : -#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not wr-prot not clean */
> : +#define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHE) /* Write protected */
> : +#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHE)  /* Not wr-prot not clean */
> :  #define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not wr-prot but clean */
> :  #define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
> :  #define	PG_FRAME	0x3fffffc0
> : 
> 
> We should audit all the PG_CACHE vs PG_CACHED stuff, and maybe change
> PG_CACHED to PG_PAGE_CACHED and PG_UNCACHED to PG_PAGE_UNCACHED...

You'd probably do better still to put all of the cache related bits under
something like PG_C_ or PG_CCA_ (the latter being "cache coherency attribute")
especially if you ever plan to add anything other than cached non-coherent and
uncached for any specific CPUs.  PG_C_ makes sense since the field is almost
always called "C" in documentation (at least See MIPS Run, the MIPS R4K User's
Guide and the MIPS32 "Privileged Resource Architecture", anyway.)


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