PERFORCE change 134549 for review

[Randall R. Stewart]

http://perforce.freebsd.org/chv.cgi?CH=134549

Change 134549 by rrs at rrs-mips2-jnpr on 2008/01/31 15:37:06

	Pulls over the TARGET_OCTEON 128 bit cache line entry stuff

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/include/cache_mipsNN.h#2 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#6 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/cache.c#2 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/cache_mipsNN.c#2 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/include/cache_mipsNN.h#2 (text+ko) ====

@@ -53,3 +53,13 @@
 void	mipsNN_pdcache_inv_range_32(vm_offset_t, vm_size_t);
 void	mipsNN_pdcache_wb_range_16(vm_offset_t, vm_size_t);
 void	mipsNN_pdcache_wb_range_32(vm_offset_t, vm_size_t);
+#ifdef TARGET_OCTEON
+void	mipsNN_icache_sync_all_128(void);
+void	mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t);
+void	mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t);
+void	mipsNN_pdcache_wbinv_all_128(void);
+void	mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t);
+void	mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t);
+void	mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t);
+void	mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t);
+#endif

==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#6 (text+ko) ====

@@ -183,6 +183,18 @@
 	mips_barrier();						\
 } struct __hack
 
+#ifdef TARGET_OCTEON
+static __inline void mips_sync_icache (void)
+{
+    __asm __volatile (
+        ".set mips64\n"
+        ".word 0x041f0000\n"
+        "nop\n"
+        ".set mips0\n"
+        : : );
+}
+#endif
+
 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cache.c#2 (text+ko) ====

@@ -51,6 +51,16 @@
 		mips_cache_ops.mco_icache_sync_range_index =
 		    mipsNN_icache_sync_range_index_32;
 		break;
+#ifdef TARGET_OCTEON
+	case 128:
+		mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
+		mips_cache_ops.mco_icache_sync_range =
+		    mipsNN_icache_sync_range_128;
+		mips_cache_ops.mco_icache_sync_range_index =
+		    mipsNN_icache_sync_range_index_128;
+		break;
+#endif
+
 #ifdef MIPS_DISABLE_L1_CACHE
 	case 0:
 		mips_cache_ops.mco_icache_sync_all = cache_noop;
@@ -96,6 +106,23 @@
 		    mips_cache_ops.mco_intern_pdcache_wb_range =
 		    mipsNN_pdcache_wb_range_32;
 		break;
+#ifdef TARGET_OCTEON
+	case 128:
+		mips_cache_ops.mco_pdcache_wbinv_all =
+		    mips_cache_ops.mco_intern_pdcache_wbinv_all =
+		    mipsNN_pdcache_wbinv_all_128;
+		mips_cache_ops.mco_pdcache_wbinv_range =
+		    mipsNN_pdcache_wbinv_range_128;
+		mips_cache_ops.mco_pdcache_wbinv_range_index =
+		    mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+		    mipsNN_pdcache_wbinv_range_index_128;
+		mips_cache_ops.mco_pdcache_inv_range =
+		    mipsNN_pdcache_inv_range_128;
+		mips_cache_ops.mco_pdcache_wb_range =
+		    mips_cache_ops.mco_intern_pdcache_wb_range =
+		    mipsNN_pdcache_wb_range_128;
+		break;
+#endif		
 #ifdef MIPS_DISABLE_L1_CACHE
 	case 0:
 		mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cache_mipsNN.c#2 (text+ko) ====

@@ -56,6 +56,13 @@
 #define	SYNC	__asm volatile("sync")
 #endif
 
+#ifdef TARGET_OCTEON
+#define SYNCI  mips_sync_icache();
+#else
+#define SYNCI
+#endif
+
+
 __asm(".set mips32");
 
 static int picache_size;
@@ -545,3 +552,54 @@
 
 	SYNC;
 }
+
+
+#ifdef TARGET_OCTEON
+
+void
+mipsNN_icache_sync_all_128(void)
+{
+        SYNCI
+}
+
+void
+mipsNN_icache_sync_range_128(vm_offset_t va, vm_size_t size)
+{
+	SYNC;
+}
+
+void
+mipsNN_icache_sync_range_index_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+
+void
+mipsNN_pdcache_wbinv_all_128(void)
+{
+}
+
+
+void
+mipsNN_pdcache_wbinv_range_128(vm_offset_t va, vm_size_t size)
+{
+	SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+void
+mipsNN_pdcache_inv_range_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+void
+mipsNN_pdcache_wb_range_128(vm_offset_t va, vm_size_t size)
+{
+	SYNC;
+}
+
+#endif