PERFORCE change 134378 for review

[Randall R. Stewart]

http://perforce.freebsd.org/chv.cgi?CH=134378

Change 134378 by rrs at rrs-mips2-jnpr on 2008/01/29 16:39:58

	Adds all the rest of the target_octeon ifdefs

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#19 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#19 (text+ko) ====

@@ -83,7 +83,7 @@
 GLOBAL(cfe_vector)
 	.space 4
 #endif
-#ifdef	CPU_OCTEON
+#if defined(TARGET_OCTEON)
 GLOBAL(app_descriptor_addr)
 	.space 8
 #endif
@@ -91,6 +91,13 @@
 	.space NBPG /* Smaller than it should be since it's temp. */
 	.align 8
 GLOBAL(topstack)
+
+	
+#if defined(TARGET_OCTEON)
+        .set mips3
+#endif
+	
+	
 	.set noreorder
 	
 	.text
@@ -99,7 +106,18 @@
 ASM_ENTRY(_start)
 VECTOR(_locore, unknown)
 	/* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */
+#if defined(TARGET_OCTEON)
+	/*
+	 * t1: Bits to set explicitly:
+	 *	Enable FPU
+	 */
+
+	/* Set these bits */
+        li	t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_SX | MIPS_SR_BEV)
 
+	/* Reset these bits */
+        li	t0, ~(MIPS_SR_DE | MIPS_SR_SOFT_RESET | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE)
+#else
 	mtc0	zero, COP_0_CAUSE_REG	# Clear soft interrupts
 
 	/*
@@ -108,13 +126,12 @@
 	 *	Boot exception vectors (firmware-provided)
 	 */
 	li	t0, (MIPS_SR_BEV | MIPS_SR_SOFT_RESET)
-
 	/*
 	 * t1: Bits to set explicitly:
 	 *	Enable FPU
 	 */
 	li	t1, MIPS_SR_COP_1_BIT
-
+#endif
 	/*
 	 * Read coprocessor 0 status register, clear bits not
 	 * preserved (namely, clearing interrupt bits), and set
@@ -126,6 +143,12 @@
 	mtc0	t2, COP_0_STATUS_REG
 	COP0_SYNC
 
+#if defined(TARGET_OCTEON)
+	/* Clear cause register. */
+	mtc0	zero, MIPS_COP_0_CAUSE
+	COP0_SYNC
+#endif
+	
 	/* Make sure KSEG0 is cached */
 	li	t0, CFG_K0_CACHED
 	mtc0	t0, MIPS_COP_0_CONFIG
@@ -175,7 +198,7 @@
 	sw	a2, _C_LABEL(cfe_vector)/* Firmware entry vector */
 no_cfe:
 #endif
-#ifdef CPU_OCTEON
+#if defined(TARGET_OCTEON)
 	la	a0, app_descriptor_addr
 	sw	a3, 0(a0)		/* Store app descriptor ptr */
 #endif
@@ -206,7 +229,8 @@
 	mtcr	t1, t2
 #endif
 
-#ifdef	CPU_OCTEON /* Maybe this is mips32/64 generic? */
+
+#if defined(TARGET_OCTEON) /* Maybe this is mips32/64 generic? */
 	.set push
 	.set mips32r2
 	rdhwr	t0, $0