PERFORCE change 134362 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=134362

Change 134362 by imp at imp_lighthouse on 2008/01/29 08:24:07

	Merge some changes from the cavium tree, lots of work needed here,
	so you should expect it not to work just yet.
	
	o Provide a simple secondary start routine for all cores that come
	  up when we're not doing SMP (I'd think it would be better to
	  pause the core, but I didn't see a way to do that).
	o Restore stack code.  TD_PCB was assumed to be 8 byte aligned,
	  but it seems to only be 4 byte aligned.  Cope by clearing bits to
	  make it 8-byte aligned.
	o On the octeon, save the app descriptor address.  The octeon code
	  wants to parse this.  This is in the same class as the YAMON and CFE
	  saving, but is it really needed?  I don't know.
	o don't li 0 when moving from zero works better.
	o Put KSEG0 into cached mode.  I don't know why the cavium code does
	  this, but maybe it is to put it into uncached mode easily.
	o Remove redundant setting of STATUS reg.

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#18 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#18 (text+ko) ====

@@ -83,6 +83,10 @@
 GLOBAL(cfe_vector)
 	.space 4
 #endif
+#ifdef	CPU_OCTEON
+GLOBAL(app_descriptor_addr)
+	.space 8
+#endif
 GLOBAL(stackspace)
 	.space NBPG /* Smaller than it should be since it's temp. */
 	.align 8
@@ -96,10 +100,6 @@
 VECTOR(_locore, unknown)
 	/* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */
 
-	# Keep firmware exception handlers until the kernel sets up its own
-	# exception handlers.
-	li	v0, SR_BOOT_EXC_VEC
-	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts.
 	mtc0	zero, COP_0_CAUSE_REG	# Clear soft interrupts
 
 	/*
@@ -125,15 +125,19 @@
 	or	t2, t1
 	mtc0	t2, COP_0_STATUS_REG
 	COP0_SYNC
-	/* Extra nops for the FPU to spin up. */
+
+	/* Make sure KSEG0 is cached */
+	li	t0, CFG_K0_CACHED
+	mtc0	t0, MIPS_COP_0_CONFIG
+	COP0_SYNC
+
+	/* Read and store the PrID FPU ID for CPU identification, if any. */
 	mfc0	t2, COP_0_STATUS_REG
-
-	/* Read and store the PrID FPU ID for CPU identification. */
 	mfc0	t0, MIPS_COP_0_PRID
 #ifndef CPU_NOFPU
 	and	t2, MIPS_SR_COP_1_BIT
 	beqz	t2, 1f
-	li	t1, 0x0
+	move	t1, zero
 	cfc1	t1, MIPS_FPU_ID
 1:
 #else
@@ -141,7 +145,7 @@
 	 * This platform has no FPU, and attempting to detect one
 	 * using the official method causes an exception.
 	 */
-	li	t1, 0x0
+	move	t1, zero
 #endif
 	sw	t0, _C_LABEL(cpu_id)
 	sw	t1, _C_LABEL(fpu_id)
@@ -171,6 +175,10 @@
 	sw	a2, _C_LABEL(cfe_vector)/* Firmware entry vector */
 no_cfe:
 #endif
+#ifdef CPU_OCTEON
+	la	a0, app_descriptor_addr
+	sw	a3, 0(a0)		/* Store app descriptor ptr */
+#endif
 
 	/*
 	 * The following needs to be done differently for each platform and
@@ -198,6 +206,18 @@
 	mtcr	t1, t2
 #endif
 
+#ifdef	CPU_OCTEON /* Maybe this is mips32/64 generic? */
+	.set push
+	.set mips32r2
+	rdhwr	t0, $0
+	.set pop
+#else
+	move	t0, zero
+#endif
+	/* Stage the secondary cpu start until later */
+	bne	t0, zero, start_secondary
+	nop
+
 #ifdef SMP
 	la	t0, _C_LABEL(__pcpu)
 	SET_CPU_PCPU(t0)
@@ -211,6 +231,12 @@
 	jal	_C_LABEL(platform_start)
 	sw	zero, START_FRAME - 8(sp)	# Zero out old fp for debugger
 
+	la      sp, _C_LABEL(thread0)
+	lw      a0, TD_PCB(sp)
+	li	t0, ~7
+	and	a0, a0, t0
+	subu    sp, a0, START_FRAME
+
 	jal	_C_LABEL(mi_startup)		# mi_startup(frame)
 	sw	zero, START_FRAME - 8(sp)	# Zero out old fp for debugger
 
@@ -231,6 +257,10 @@
 	nop
 	jal	_C_LABEL(smp_init_secondary)
 	nop
+#else
+start_secondary:
+	b	start_secondary
+	nop
 #endif
 
 VECTOR_END(_locore)