PERFORCE change 132345 for review
Warner Losh
imp at FreeBSD.org
Wed Jan 2 14:42:29 PST 2008
http://perforce.freebsd.org/chv.cgi?CH=132345
Change 132345 by imp at imp_paco-paco on 2008/01/02 22:41:37
Harmonize where we define things. This might not be perfect,
but it gets us going... Might need to clean it up...
Affected files ...
.. //depot/projects/mips2-jnpr/src/sys/mips/include/asmacros.h#2 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#4 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#4 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/include/cpuregs.h#2 edit
Differences ...
==== //depot/projects/mips2-jnpr/src/sys/mips/include/asmacros.h#2 (text+ko) ====
==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#4 (text+ko) ====
@@ -50,11 +50,6 @@
#include <machine/psl.h>
#include <machine/endian.h>
-#define MIPS_KUSEG_ADDR 0x0
-#define MIPS_KSEG0_START MIPS_CACHED_MEMORY_ADDR
-#define MIPS_KSEG1_START MIPS_UNCACHED_MEMORY_ADDR
-#define MIPS_KSEG2_START 0xc0000000
-
#define MIPS_CACHED_MEMORY_ADDR 0x80000000
#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000
#define MIPS_MAX_MEM_ADDR 0xbe000000
==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#4 (text+ko) ====
@@ -35,6 +35,216 @@
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
+#include <sys/types.h>
+#include <machine/cpuregs.h>
+
+/*
+ * These functions are required by user-land atomi ops
+ */
+
+static __inline void
+mips_barrier(void)
+{
+ __asm __volatile (".set noreorder\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set reorder\n\t"
+ : : : "memory");
+}
+
+static __inline void
+mips_wbflush(void)
+{
+ __asm __volatile ("sync" : : : "memory");
+ mips_barrier();
+#if 0
+ __asm __volatile("mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
+ : : "r" (flag));
+#endif
+}
+
+static __inline void
+mips_read_membar(void)
+{
+ /* Nil */
+}
+
+static __inline void
+mips_write_membar(void)
+{
+ mips_wbflush();
+}
+
+#ifdef _KERNEL
+
+static __inline void
+mips_tlbp(void)
+{
+ __asm __volatile ("tlbp");
+ mips_barrier();
+#if 0
+ register_t ret;
+ register_t tmp;
+
+ __asm __volatile("mfc0 %0, $12\n" /* MIPS_COP_0_STATUS */
+ "and %1, %0, $~1\n" /* MIPS_SR_INT_IE */
+ "mtc0 %1, $12\n" /* MIPS_COP_0_STATUS */
+ : "=r" (ret), "=r" (tmp));
+ return (ret);
+#endif
+}
+
+static __inline void
+mips_tlbr(void)
+{
+ __asm __volatile ("tlbr");
+ mips_barrier();
+}
+
+static __inline void
+mips_tlbwi(void)
+{
+ __asm __volatile ("tlbwi");
+ mips_barrier();
+#if 0
+ __asm __volatile("mfc %0, $12\n" /* MIPS_COP_0_STATUS */
+ "or %0, %0, $1\n" /* MIPS_SR_INT_IE */
+ "mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
+ : "=r" (tmp));
+#endif
+}
+
+static __inline void
+mips_tlbwr(void)
+{
+ __asm __volatile ("tlbwr");
+ mips_barrier();
+}
+
+
+#if 0 /* XXX mips64 */
+
+#define MIPS_RDRW64_COP0(n,r) \
+static __inline u_int64_t \
+mips_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n (u_int64_t a0) \
+{ \
+ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
+MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
+
+#undef MIPS_RDRW64_COP0
+#endif
+
+#define MIPS_RDRW32_COP0(n,r) \
+static __inline u_int32_t \
+mips_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n (u_int32_t a0) \
+{ \
+ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
+MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
+MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
+MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
+MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
+MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
+MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
+
+/* XXX: Some of these registers are specific to MIPS32. */
+MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
+MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
+MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
+MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
+MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
+
+static __inline u_int32_t
+mips_rd_config_sel1(void)
+{
+ int v0;
+ __asm __volatile("mfc0 %[v0], $16, 1 ;"
+ : [v0] "=&r" (v0));
+ mips_barrier();
+ return (v0);
+}
+
+#undef MIPS_RDRW32_COP0
+
+static __inline register_t
+intr_disable(void)
+{
+ register_t s;
+
+ s = mips_rd_status();
+ mips_wr_status(s & ~MIPS_SR_INT_IE);
+
+ return (s);
+}
+
+static __inline register_t
+intr_enable(void)
+{
+ register_t s;
+
+ s = mips_rd_status();
+ mips_wr_status(s | MIPS_SR_INT_IE);
+
+ return (s);
+}
+
+#define intr_restore(s) mips_wr_status((s))
+
+static __inline void
+breakpoint(void)
+{
+ __asm __volatile ("break");
+}
+
+#endif /* _KERNEL */
+
#define readb(va) (*(volatile u_int8_t *) (va))
#define readw(va) (*(volatile u_int16_t *) (va))
#define readl(va) (*(volatile u_int32_t *) (va))
@@ -70,10 +280,6 @@
#define _swap_(x) (((x) >> 24) | ((x) << 24) | \
(((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8))
-#define intr_disable disableintr
-#define intr_restore(s) restoreintr(s)
-#define intr_enable enableintr
-
static __inline void __out32rb(volatile u_int32_t *, u_int32_t);
static __inline void __out16rb(volatile u_int16_t *, u_int16_t);
static __inline u_int32_t __in32rb(volatile u_int32_t *);
@@ -124,6 +330,5 @@
void outsw(u_int16_t *, const u_int16_t *,int);
void outsl(u_int32_t *, const u_int32_t *,int);
u_int loadandclear(volatile u_int *addr);
-int breakpoint(void);
#endif /* !_MACHINE_CPUFUNC_H_ */
==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpuregs.h#2 (text+ko) ====
@@ -88,13 +88,6 @@
#define MIPS_MAX_MEM_ADDR 0xbe000000
#define MIPS_RESERVED_ADDR 0xbfc80000
-#define MIPS_PHYS_MASK 0x1fffffff
-
-#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
-#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
-#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
-#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
-
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
#define MIPS3_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
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