PERFORCE change 136066 for review
Marcel Moolenaar
marcel at FreeBSD.org
Sun Feb 24 05:49:15 UTC 2008
http://perforce.freebsd.org/chv.cgi?CH=136066
Change 136066 by marcel at marcel_xcllnt on 2008/02/24 05:48:57
Unify <machine/pcpu.h>
This is a bit tricky. The PCPU on Book E is much bigger
then the PCPU on AIM. The union trick would pessimize
AIM too much. On top of that, PCPU_MD_FIELDS needs to
be defined for MI code. We're going to have to test for
AIM or E500 here. So, we define all fields separately
for AIM and BOOKE so that the co-exist and then test
the CPU type for how to define PCPU_MD_FIELDS.
To support LINT, we check for COMPILING_LINT and define
PCPU_MD_FIELDS to be the union of AIM and BOOKE fields.
Affected files ...
.. //depot/projects/e500/sys/powerpc/aim/trap_subr.S#5 edit
.. //depot/projects/e500/sys/powerpc/booke/trap_subr.S#5 edit
.. //depot/projects/e500/sys/powerpc/include/pcpu.h#4 edit
.. //depot/projects/e500/sys/powerpc/powerpc/genassym.c#6 edit
Differences ...
==== //depot/projects/e500/sys/powerpc/aim/trap_subr.S#5 (text+ko) ====
@@ -140,8 +140,8 @@
stw %r29, FRAME_29+8(%r1); \
stw %r30, FRAME_30+8(%r1); \
stw %r31, FRAME_31+8(%r1); \
- lwz %r28,(savearea+CPUSAVE_DAR)(%r2); /* saved DAR */ \
- lwz %r29,(savearea+CPUSAVE_DSISR)(%r2);/* saved DSISR */ \
+ lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
+ lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
mfxer %r3; \
@@ -272,8 +272,8 @@
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mfdar %r30
mfdsisr %r31
- stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
- stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
+ stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
+ stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
mfsprg1 %r1 /* restore SP, in case of branch */
mflr %r28 /* save LR */
mfcr %r29 /* save CR */
@@ -356,8 +356,8 @@
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mfdar %r30
mfdsisr %r31
- stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
- stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
+ stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
+ stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
#ifdef KDB
/* Try and detect a kernel stack overflow */
@@ -373,10 +373,10 @@
/* Now convert this DSI into a DDB trap. */
GET_CPUINFO(%r1)
- lwz %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1) /* get DAR */
- stw %r30,(PC_DBSAVE +CPUSAVE_DAR)(%r1) /* save DAR */
- lwz %r30,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1) /* get DSISR */
- lwz %r30,(PC_DBSAVE +CPUSAVE_DSISR)(%r1) /* save DSISR */
+ lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
+ stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
+ lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
+ lwz %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
==== //depot/projects/e500/sys/powerpc/booke/trap_subr.S#5 (text+ko) ====
@@ -113,8 +113,8 @@
stw %r31, (savearea+CPUSAVE_R31)(%r1); \
mfdear %r30; \
mfesr %r31; \
- stw %r30, (savearea+CPUSAVE_DEAR)(%r1); \
- stw %r31, (savearea+CPUSAVE_ESR)(%r1) ; \
+ stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \
+ stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \
mfspr %r30, isrr0; \
mfspr %r31, isrr1; /* MSR at interrupt time */ \
stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \
@@ -136,8 +136,8 @@
stw %r31, (savearea+CPUSAVE_R31)(%r1); \
mfdear %r30; \
mfesr %r31; \
- stw %r30, (savearea+CPUSAVE_DEAR)(%r1); \
- stw %r31, (savearea+CPUSAVE_ESR)(%r1) ; \
+ stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \
+ stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \
mfspr %r30, isrr0; \
mfspr %r31, isrr1; /* MSR at interrupt time */ \
stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \
@@ -196,8 +196,8 @@
/* save R3-31 */ \
stmw %r3, FRAME_3+8(%r1) ; \
/* save DEAR, ESR */ \
- lwz %r28, (savearea+CPUSAVE_DEAR)(%r2); \
- lwz %r29, (savearea+CPUSAVE_ESR)(%r2); \
+ lwz %r28, (savearea+CPUSAVE_BOOKE_DEAR)(%r2); \
+ lwz %r29, (savearea+CPUSAVE_BOOKE_ESR)(%r2); \
stw %r28, FRAME_BOOKE_DEAR+8(1); \
stw %r29, FRAME_BOOKE_ESR+8(1); \
/* save XER, CTR, exc number */ \
@@ -259,27 +259,27 @@
mtsprg6 %r29; \
/* calculate TLB nesting level and TLBSAVE instance address */ \
GET_CPUINFO(%r1); /* Per-cpu structure */ \
- lwz %r28, PC_TLB_LEVEL(%r1); \
+ lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \
rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \
addi %r28, %r28, 1; \
- stw %r28, PC_TLB_LEVEL(%r1); \
- addi %r29, %r29, PC_TLBSAVE at l; \
+ stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \
+ addi %r29, %r29, PC_BOOKE_TLBSAVE at l; \
add %r1, %r1, %r29; /* current TLBSAVE ptr */ \
\
/* save R20-31 */ \
mfsprg5 %r28; \
mfsprg6 %r29; \
- stmw %r20, (TLBSAVE_R20)(%r1); \
+ stmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \
/* save LR, CR */ \
mflr %r30; \
mfcr %r31; \
- stw %r30, (TLBSAVE_LR)(%r1); \
- stw %r31, (TLBSAVE_CR)(%r1); \
+ stw %r30, (TLBSAVE_BOOKE_LR)(%r1); \
+ stw %r31, (TLBSAVE_BOOKE_CR)(%r1); \
/* save SRR0-1 */ \
mfsrr0 %r30; /* execution addr at interrupt time */ \
mfsrr1 %r31; /* MSR at interrupt time*/ \
- stw %r30, (TLBSAVE_SRR0)(%r1); /* save SRR0 */ \
- stw %r31, (TLBSAVE_SRR1)(%r1); /* save SRR1 */ \
+ stw %r30, (TLBSAVE_BOOKE_SRR0)(%r1); /* save SRR0 */ \
+ stw %r31, (TLBSAVE_BOOKE_SRR1)(%r1); /* save SRR1 */ \
isync; \
mfsprg4 %r1
@@ -292,25 +292,25 @@
mtsprg4 %r1; /* Save SP */ \
GET_CPUINFO(%r1); /* Per-cpu structure */ \
/* calculate TLB nesting level and TLBSAVE instance addr */ \
- lwz %r28, PC_TLB_LEVEL(%r1); \
+ lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \
subi %r28, %r28, 1; \
- stw %r28, PC_TLB_LEVEL(%r1); \
+ stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \
rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \
- addi %r29, %r29, PC_TLBSAVE at l; \
+ addi %r29, %r29, PC_BOOKE_TLBSAVE at l; \
add %r1, %r1, %r29; \
\
/* restore LR, CR */ \
- lwz %r30, (TLBSAVE_LR)(%r1); \
- lwz %r31, (TLBSAVE_CR)(%r1); \
+ lwz %r30, (TLBSAVE_BOOKE_LR)(%r1); \
+ lwz %r31, (TLBSAVE_BOOKE_CR)(%r1); \
mtlr %r30; \
mtcr %r31; \
/* restore SRR0-1 */ \
- lwz %r30, (TLBSAVE_SRR0)(%r1); \
- lwz %r31, (TLBSAVE_SRR1)(%r1); \
+ lwz %r30, (TLBSAVE_BOOKE_SRR0)(%r1); \
+ lwz %r31, (TLBSAVE_BOOKE_SRR1)(%r1); \
mtsrr0 %r30; \
mtsrr1 %r31; \
/* restore R20-31 */ \
- lmw %r20, (TLBSAVE_R20)(%r1); \
+ lmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \
mfsprg4 %r1
@@ -338,8 +338,8 @@
* Critical input interrupt
****************************************/
INTERRUPT(int_critical_input)
- STANDARD_PROLOG(SPR_SPRG2, PC_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
- FRAME_SETUP(SPR_SPRG2, PC_CRITSAVE, EXC_CRIT)
+ STANDARD_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
+ FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT)
addi %r3, %r1, 8
bl CNAME(powerpc_crit_interrupt)
FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1)
@@ -350,8 +350,8 @@
* Machine check interrupt
****************************************/
INTERRUPT(int_machine_check)
- STANDARD_PROLOG(SPR_SPRG3, PC_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1)
- FRAME_SETUP(SPR_SPRG3, PC_MCHKSAVE, EXC_MCHK)
+ STANDARD_PROLOG(SPR_SPRG3, PC_BOOKE_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1)
+ FRAME_SETUP(SPR_SPRG3, PC_BOOKE_MCHKSAVE, EXC_MCHK)
addi %r3, %r1, 8
bl CNAME(powerpc_mchk_interrupt)
FRAME_LEAVE(SPR_MCSRR0, SPR_MCSRR1)
@@ -718,9 +718,9 @@
* Debug interrupt
****************************************/
INTERRUPT(int_debug)
- STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
- FRAME_SETUP(SPR_SPRG2, PC_CRITSAVE, EXC_DEBUG)
- lwz %r3, (PC_CRITSAVE+CPUSAVE_SRR0)(%r2);
+ STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
+ FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG)
+ lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r2);
lis %r4, interrupt_vector_base at ha
addi %r4, %r4, interrupt_vector_base at l
cmplw cr0, %r3, %r4
@@ -734,9 +734,9 @@
rlwinm %r3,%r3,0,23,21
stw %r3, FRAME_SRR1+8(%r1);
/* Restore srr0 and srr1 as they could have been clobbered. */
- lwz %r3, (PC_CRITSAVE+CPUSAVE_SRR0+8)(%r2);
+ lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r2);
mtspr SPR_SRR0, %r3
- lwz %r4, (PC_CRITSAVE+CPUSAVE_SRR1+8)(%r2);
+ lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r2);
mtspr SPR_SRR1, %r4
b 9f
1:
@@ -812,8 +812,8 @@
mfdear %r30
mfesr %r31
- stw %r30, (PC_DBSAVE+CPUSAVE_DEAR)(%r3)
- stw %r31, (PC_DBSAVE+CPUSAVE_ESR)(%r3)
+ stw %r30, (PC_DBSAVE+CPUSAVE_BOOKE_DEAR)(%r3)
+ stw %r31, (PC_DBSAVE+CPUSAVE_BOOKE_ESR)(%r3)
mfsrr0 %r30
mfsrr1 %r31
==== //depot/projects/e500/sys/powerpc/include/pcpu.h#4 (text+ko) ====
@@ -39,59 +39,70 @@
#define PCPU_MD_COMMON_FIELDS \
int pc_inside_intr; \
struct pmap *pc_curpmap; /* current pmap */ \
- struct thread *pc_fputhread; /* current fpu user */ \
+ struct thread *pc_fputhread; /* current fpu user */ \
register_t pc_tempsave[CPUSAVE_LEN]; \
register_t pc_disisave[CPUSAVE_LEN]; \
register_t pc_dbsave[CPUSAVE_LEN];
-#if defined(AIM)
-#define PCPU_MD_FIELDS PCPU_MD_COMMON_FIELDS
-#else
+#define PCPU_MD_AIM_FIELDS
-#define TLBSAVE_LEN 16
-#define TLB_NESTED_MAX 3
+#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
+#define BOOKE_TLB_MAXNEST 3
+#define BOOKE_TLB_SAVELEN 16
+#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
-#define PCPU_MD_FIELDS \
- PCPU_MD_COMMON_FIELDS \
- register_t pc_critsave[CPUSAVE_LEN + 2]; \
- register_t pc_mchksave[CPUSAVE_LEN]; \
- register_t pc_tlbsave[TLBSAVE_LEN*TLB_NESTED_MAX]; \
- register_t pc_tlb_level;
-#endif
+#define PCPU_MD_BOOKE_FIELDS \
+ register_t pc_booke_critsave[BOOKE_CRITSAVE_LEN]; \
+ register_t pc_booke_mchksave[CPUSAVE_LEN]; \
+ register_t pc_booke_tlbsave[BOOKE_TLBSAVE_LEN]; \
+ register_t pc_booke_tlb_level;
/* Definitions for register offsets within the exception tmp save areas */
#define CPUSAVE_R28 0 /* where r28 gets saved */
#define CPUSAVE_R29 1 /* where r29 gets saved */
#define CPUSAVE_R30 2 /* where r30 gets saved */
#define CPUSAVE_R31 3 /* where r31 gets saved */
-#if defined(AIM)
-#define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */
-#define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */
-#else
-#define CPUSAVE_DEAR 4 /* where SPR_DEAR gets saved */
-#define CPUSAVE_ESR 5 /* where SPR_ESR gets saved */
-#endif
+#define CPUSAVE_AIM_DAR 4 /* where SPR_DAR gets saved */
+#define CPUSAVE_AIM_DSISR 5 /* where SPR_DSISR gets saved */
+#define CPUSAVE_BOOKE_DEAR 4 /* where SPR_DEAR gets saved */
+#define CPUSAVE_BOOKE_ESR 5 /* where SPR_ESR gets saved */
#define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
#define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
-/* TLBSAVE is more elaborate */
-#if !defined(AIM)
-#define TLBSAVE_LR 0
-#define TLBSAVE_CR 1
-#define TLBSAVE_SRR0 2
-#define TLBSAVE_SRR1 3
-#define TLBSAVE_R20 4
-#define TLBSAVE_R21 5
-#define TLBSAVE_R22 6
-#define TLBSAVE_R23 7
-#define TLBSAVE_R24 8
-#define TLBSAVE_R25 9
-#define TLBSAVE_R26 10
-#define TLBSAVE_R27 11
-#define TLBSAVE_R28 12
-#define TLBSAVE_R29 13
-#define TLBSAVE_R30 14
-#define TLBSAVE_R31 15
+/* Book-E TLBSAVE is more elaborate */
+#define TLBSAVE_BOOKE_LR 0
+#define TLBSAVE_BOOKE_CR 1
+#define TLBSAVE_BOOKE_SRR0 2
+#define TLBSAVE_BOOKE_SRR1 3
+#define TLBSAVE_BOOKE_R20 4
+#define TLBSAVE_BOOKE_R21 5
+#define TLBSAVE_BOOKE_R22 6
+#define TLBSAVE_BOOKE_R23 7
+#define TLBSAVE_BOOKE_R24 8
+#define TLBSAVE_BOOKE_R25 9
+#define TLBSAVE_BOOKE_R26 10
+#define TLBSAVE_BOOKE_R27 11
+#define TLBSAVE_BOOKE_R28 12
+#define TLBSAVE_BOOKE_R29 13
+#define TLBSAVE_BOOKE_R30 14
+#define TLBSAVE_BOOKE_R31 15
+
+#ifndef COMPILING_LINT
+#ifdef AIM
+#define PCPU_MD_FIELDS \
+ PCPU_MD_COMMON_FIELDS \
+ PCPU_MD_AIM_FIELDS
+#endif
+#ifdef E500
+#define PCPU_MD_FIELDS \
+ PCPU_MD_COMMON_FIELDS \
+ PCPU_MD_BOOKE_FIELDS
+#endif
+#else
+#define PCPU_MD_FIELDS \
+ PCPU_MD_COMMON_FIELDS \
+ PCPU_MD_AIM_FIELDS \
+ PCPU_MD_BOOKE_FIELDS
#endif
#define PCPUP ((struct pcpu *) powerpc_get_pcpup())
==== //depot/projects/e500/sys/powerpc/powerpc/genassym.c#6 (text+ko) ====
@@ -61,44 +61,41 @@
ASSYM(PC_TEMPSAVE, offsetof(struct pcpu, pc_tempsave));
ASSYM(PC_DISISAVE, offsetof(struct pcpu, pc_disisave));
ASSYM(PC_DBSAVE, offsetof(struct pcpu, pc_dbsave));
-#if defined(E500)
-ASSYM(PC_CRITSAVE, offsetof(struct pcpu, pc_critsave));
-ASSYM(PC_MCHKSAVE, offsetof(struct pcpu, pc_mchksave));
-ASSYM(PC_TLBSAVE, offsetof(struct pcpu, pc_tlbsave));
-ASSYM(PC_TLB_LEVEL, offsetof(struct pcpu, pc_tlb_level));
+
+#ifdef E500
+ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke_critsave));
+ASSYM(PC_BOOKE_MCHKSAVE, offsetof(struct pcpu, pc_booke_mchksave));
+ASSYM(PC_BOOKE_TLBSAVE, offsetof(struct pcpu, pc_booke_tlbsave));
+ASSYM(PC_BOOKE_TLB_LEVEL, offsetof(struct pcpu, pc_booke_tlb_level));
#endif
ASSYM(CPUSAVE_R28, CPUSAVE_R28*4);
ASSYM(CPUSAVE_R29, CPUSAVE_R29*4);
ASSYM(CPUSAVE_R30, CPUSAVE_R30*4);
ASSYM(CPUSAVE_R31, CPUSAVE_R31*4);
-#if defined(AIM)
-ASSYM(CPUSAVE_DAR, CPUSAVE_DAR*4);
-ASSYM(CPUSAVE_DSISR, CPUSAVE_DSISR*4);
-#elif defined(E500)
-ASSYM(CPUSAVE_DEAR, CPUSAVE_DEAR*4);
-ASSYM(CPUSAVE_ESR, CPUSAVE_ESR*4);
-#endif
ASSYM(CPUSAVE_SRR0, CPUSAVE_SRR0*4);
ASSYM(CPUSAVE_SRR1, CPUSAVE_SRR1*4);
-#if defined(E500)
-ASSYM(TLBSAVE_LR, TLBSAVE_LR*4);
-ASSYM(TLBSAVE_CR, TLBSAVE_CR*4);
-ASSYM(TLBSAVE_SRR0, TLBSAVE_SRR0*4);
-ASSYM(TLBSAVE_SRR1, TLBSAVE_SRR1*4);
-ASSYM(TLBSAVE_R20, TLBSAVE_R20*4);
-ASSYM(TLBSAVE_R21, TLBSAVE_R21*4);
-ASSYM(TLBSAVE_R22, TLBSAVE_R22*4);
-ASSYM(TLBSAVE_R23, TLBSAVE_R23*4);
-ASSYM(TLBSAVE_R24, TLBSAVE_R24*4);
-ASSYM(TLBSAVE_R25, TLBSAVE_R25*4);
-ASSYM(TLBSAVE_R26, TLBSAVE_R26*4);
-ASSYM(TLBSAVE_R27, TLBSAVE_R27*4);
-ASSYM(TLBSAVE_R28, TLBSAVE_R28*4);
-ASSYM(TLBSAVE_R29, TLBSAVE_R29*4);
-ASSYM(TLBSAVE_R30, TLBSAVE_R30*4);
-ASSYM(TLBSAVE_R31, TLBSAVE_R31*4);
-#endif
+ASSYM(CPUSAVE_AIM_DAR, CPUSAVE_AIM_DAR*4);
+ASSYM(CPUSAVE_AIM_DSISR, CPUSAVE_AIM_DSISR*4);
+ASSYM(CPUSAVE_BOOKE_DEAR, CPUSAVE_BOOKE_DEAR*4);
+ASSYM(CPUSAVE_BOOKE_ESR, CPUSAVE_BOOKE_ESR*4);
+
+ASSYM(TLBSAVE_BOOKE_LR, TLBSAVE_BOOKE_LR*4);
+ASSYM(TLBSAVE_BOOKE_CR, TLBSAVE_BOOKE_CR*4);
+ASSYM(TLBSAVE_BOOKE_SRR0, TLBSAVE_BOOKE_SRR0*4);
+ASSYM(TLBSAVE_BOOKE_SRR1, TLBSAVE_BOOKE_SRR1*4);
+ASSYM(TLBSAVE_BOOKE_R20, TLBSAVE_BOOKE_R20*4);
+ASSYM(TLBSAVE_BOOKE_R21, TLBSAVE_BOOKE_R21*4);
+ASSYM(TLBSAVE_BOOKE_R22, TLBSAVE_BOOKE_R22*4);
+ASSYM(TLBSAVE_BOOKE_R23, TLBSAVE_BOOKE_R23*4);
+ASSYM(TLBSAVE_BOOKE_R24, TLBSAVE_BOOKE_R24*4);
+ASSYM(TLBSAVE_BOOKE_R25, TLBSAVE_BOOKE_R25*4);
+ASSYM(TLBSAVE_BOOKE_R26, TLBSAVE_BOOKE_R26*4);
+ASSYM(TLBSAVE_BOOKE_R27, TLBSAVE_BOOKE_R27*4);
+ASSYM(TLBSAVE_BOOKE_R28, TLBSAVE_BOOKE_R28*4);
+ASSYM(TLBSAVE_BOOKE_R29, TLBSAVE_BOOKE_R29*4);
+ASSYM(TLBSAVE_BOOKE_R30, TLBSAVE_BOOKE_R30*4);
+ASSYM(TLBSAVE_BOOKE_R31, TLBSAVE_BOOKE_R31*4);
ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock));
ASSYM(MTX_RECURSECNT, offsetof(struct mtx, mtx_recurse));
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