PERFORCE change 135810 for review
Randall R. Stewart
rrs at FreeBSD.org
Wed Feb 20 18:00:51 UTC 2008
http://perforce.freebsd.org/chv.cgi?CH=135810
Change 135810 by rrs at rrs-mips2-jnpr on 2008/02/20 18:00:04
s9indent of file
Affected files ...
.. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#11 edit
Differences ...
==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#11 (text+ko) ====
@@ -197,20 +197,24 @@
-static __inline u_int32_t mips_rd_ebase(void)
+static __inline u_int32_t
+mips_rd_ebase(void)
{
int v0;
__asm __volatile("mfc0 %[v0], $15, 1 ;"
- : [v0] "=&r" (v0));
+ : [v0] "=&r"(v0));
+
mips_barrier();
return (v0);
}
-static __inline void mips_wr_ebase(u_int32_t a0)
+static __inline void
+mips_wr_ebase(u_int32_t a0)
{
__asm __volatile("mtc0 %[a0], $15, 1 ;"
- :
- : [a0] "r"(a0));
+ :
+ : [a0] "r"(a0));
+
mips_barrier();
}
@@ -219,225 +223,248 @@
* Perform a board-level soft-reset.
* Note that this is not emulated by gxemul.
*/
-void octeon_reset (void)
+void
+octeon_reset(void)
{
- void (*reset_func)(void) = (void (*)(void) )0x1fc00000;
- reset_func();
+ void (*reset_func) (void)= (void (*) (void))0x1fc00000;
+
+ reset_func();
}
-static inline uint32_t octeon_disable_interrupts (void)
+static inline uint32_t
+octeon_disable_interrupts(void)
{
- uint32_t status_bits;
+ uint32_t status_bits;
- status_bits = mips_rd_status();
- mips_wr_status(status_bits & ~MIPS_SR_INT_IE);
- return (status_bits);
+ status_bits = mips_rd_status();
+ mips_wr_status(status_bits & ~MIPS_SR_INT_IE);
+ return (status_bits);
}
-static inline void octeon_set_interrupts (uint32_t status_bits)
+static inline void
+octeon_set_interrupts(uint32_t status_bits)
{
- mips_wr_status(status_bits);
+ mips_wr_status(status_bits);
}
-void octeon_led_write_char (int char_position, char val)
+void
+octeon_led_write_char(int char_position, char val)
{
- uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
- if (!octeon_board_real()) return;
+ if (!octeon_board_real())
+ return;
- char_position &= 0x7; /* only 8 chars */
- ptr += char_position;
- oct_write8_x8(ptr, val);
+ char_position &= 0x7; /* only 8 chars */
+ ptr += char_position;
+ oct_write8_x8(ptr, val);
}
-void octeon_led_write_char0 (char val)
+void
+octeon_led_write_char0(char val)
{
- uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
- if (!octeon_board_real()) return;
+ if (!octeon_board_real())
+ return;
- oct_write8_x8(ptr, val);
+ oct_write8_x8(ptr, val);
}
-void octeon_led_write_hexchar (int char_position, char hexval)
+void
+octeon_led_write_hexchar(int char_position, char hexval)
{
- uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
- char char1, char2;
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ char char1, char2;
- if (!octeon_board_real()) return;
+ if (!octeon_board_real())
+ return;
- char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7';
- char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7';
- char_position &= 0x7; /* only 8 chars */
- if (char_position > 6) char_position = 6;
- ptr += char_position;
- oct_write8_x8(ptr, char1);
- ptr++;
- oct_write8_x8(ptr, char2);
+ char1 = (hexval >> 4) & 0x0f;
+ char1 = (char1 < 10) ? char1 + '0' : char1 + '7';
+ char2 = (hexval & 0x0f);
+ char2 = (char2 < 10) ? char2 + '0' : char2 + '7';
+ char_position &= 0x7; /* only 8 chars */
+ if (char_position > 6)
+ char_position = 6;
+ ptr += char_position;
+ oct_write8_x8(ptr, char1);
+ ptr++;
+ oct_write8_x8(ptr, char2);
}
-void octeon_led_write_string (const char *str)
+void
+octeon_led_write_string(const char *str)
{
- uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
- int i;
+ uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
+ int i;
- if (!octeon_board_real()) return;
+ if (!octeon_board_real())
+ return;
- for (i=0; i<8; i++, ptr++) {
- if (str && *str) {
- oct_write8_x8(ptr, *str++);
- } else {
- oct_write8_x8(ptr, ' ');
- }
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
- }
+ for (i = 0; i < 8; i++, ptr++) {
+ if (str && *str) {
+ oct_write8_x8(ptr, *str++);
+ } else {
+ oct_write8_x8(ptr, ' ');
+ }
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ }
}
-static char progress[8] = { 'F', 'R', 'E', 'E', 'B', 'S', 'D', '!'};
+static char progress[8] = {'F', 'R', 'E', 'E', 'B', 'S', 'D', '!'};
-int prog_count=0;
+int prog_count = 0;
-void octeon_led_run_wheel (void)
+void
+octeon_led_run_wheel(void)
{
- if (!octeon_board_real()) return;
+ if (!octeon_board_real())
+ return;
+
+ if (prog_count > 7) {
+ int i;
- if(prog_count > 7) {
- int i;
- /* blank display and reset */
- prog_count = 0;
- for(i=0; i<8; i++) {
- octeon_led_write_char(i, ' ');
- }
- } else {
- octeon_led_write_char(prog_count, progress[prog_count]);
- prog_count += 1;
- }
+ /* blank display and reset */
+ prog_count = 0;
+ for (i = 0; i < 8; i++) {
+ octeon_led_write_char(i, ' ');
+ }
+ } else {
+ octeon_led_write_char(prog_count, progress[prog_count]);
+ prog_count += 1;
+ }
}
-#define LSR_DATAREADY 0x01 /* Data ready */
-#define LSR_THRE 0x20 /* Transmit holding register empty */
-#define LSR_TEMT 0x40 /* Transmitter Empty. THR, TSR & FIFO */
-#define USR_TXFIFO_NOTFULL 0x02 /* Uart TX FIFO Not full */
+#define LSR_DATAREADY 0x01 /* Data ready */
+#define LSR_THRE 0x20 /* Transmit holding register empty */
+#define LSR_TEMT 0x40 /* Transmitter Empty. THR, TSR & FIFO */
+#define USR_TXFIFO_NOTFULL 0x02 /* Uart TX FIFO Not full */
/*
* octeon_uart_write_byte
- *
+ *
* Put out a single byte off of uart port.
*/
-void octeon_uart_write_byte (int uart_index, uint8_t ch)
+void
+octeon_uart_write_byte(int uart_index, uint8_t ch)
{
- uint64_t val, val2;
- if ((uart_index < 0) || (uart_index > 1)) {
- return;
- }
+ uint64_t val, val2;
- while (1) {
- val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
- val2 = oct_read64(OCTEON_MIO_UART0_USR + (uart_index * 0x400));
- if ((((uint8_t) val) & LSR_THRE) ||
- (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
- break;
- }
- }
+ if ((uart_index < 0) || (uart_index > 1)) {
+ return;
+ }
+ while (1) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
+ val2 = oct_read64(OCTEON_MIO_UART0_USR + (uart_index * 0x400));
+ if ((((uint8_t) val) & LSR_THRE) ||
+ (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
+ break;
+ }
+ }
- /* Write the byte */
-// oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
- oct_write64(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
+ /* Write the byte */
+ //oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
+ oct_write64(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
- /* Force Flush the IOBus */
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
}
-void octeon_uart_write_byte0 (uint8_t ch)
+void
+octeon_uart_write_byte0(uint8_t ch)
{
- uint64_t val, val2;
+ uint64_t val, val2;
- while (1) {
- val = oct_read64(OCTEON_MIO_UART0_LSR);
- val2 = oct_read64(OCTEON_MIO_UART0_USR);
- if ((((uint8_t) val) & LSR_THRE) ||
- (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
- break;
- }
- }
+ while (1) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR);
+ val2 = oct_read64(OCTEON_MIO_UART0_USR);
+ if ((((uint8_t) val) & LSR_THRE) ||
+ (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
+ break;
+ }
+ }
- /* Write the byte */
-// oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch);
- oct_write64(OCTEON_MIO_UART0_THR, (uint64_t) ch);
+ /* Write the byte */
+ //oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch);
+ oct_write64(OCTEON_MIO_UART0_THR, (uint64_t) ch);
- /* Force Flush the IOBus */
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
}
/*
* octeon_uart_write_string
- *
+ *
*/
-void octeon_uart_write_string (int uart_index, const char *str)
+void
+octeon_uart_write_string(int uart_index, const char *str)
{
- /* Just loop writing one byte at a time */
-
- while (*str)
- {
- octeon_uart_write_byte(uart_index, *str);
- if (*str == '\n') {
- octeon_uart_write_byte(uart_index, '\r');
- }
- str++;
- }
- }
+ /* Just loop writing one byte at a time */
+
+ while (*str) {
+ octeon_uart_write_byte(uart_index, *str);
+ if (*str == '\n') {
+ octeon_uart_write_byte(uart_index, '\r');
+ }
+ str++;
+ }
+}
static char wstr[30];
-void octeon_led_write_hex (uint32_t wl)
+void
+octeon_led_write_hex(uint32_t wl)
{
- char nbuf[80];
+ char nbuf[80];
- sprintf(nbuf, "%X", wl);
- octeon_led_write_string(nbuf);
+ sprintf(nbuf, "%X", wl);
+ octeon_led_write_string(nbuf);
}
-void octeon_uart_write_hex2 (uint32_t wl, uint32_t wh)
+void
+octeon_uart_write_hex2(uint32_t wl, uint32_t wh)
{
- sprintf(wstr, "0x%X-0x%X ", wh, wl);
- octeon_uart_write_string(0, wstr);
+ sprintf(wstr, "0x%X-0x%X ", wh, wl);
+ octeon_uart_write_string(0, wstr);
}
-void octeon_uart_write_hex (uint32_t wl)
+void
+octeon_uart_write_hex(uint32_t wl)
{
- sprintf(wstr, " 0x%X ", wl);
- octeon_uart_write_string(0, wstr);
+ sprintf(wstr, " 0x%X ", wl);
+ octeon_uart_write_string(0, wstr);
}
/*
* octeon_wait_uart_flush
*/
-void octeon_wait_uart_flush (int uart_index, uint8_t ch)
+void
+octeon_wait_uart_flush(int uart_index, uint8_t ch)
{
- uint64_t val;
- int64_t val3;
- uint32_t cpu_status_bits;
+ uint64_t val;
+ int64_t val3;
+ uint32_t cpu_status_bits;
- if ((uart_index < 0) || (uart_index > 1)) {
- return;
- }
-
- cpu_status_bits = octeon_disable_interrupts();
- /* Force Flush the IOBus */
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
- for (val3 = 0xfffffffff; val3 > 0; val3--) {
- val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
- if (((uint8_t) val) & LSR_TEMT) {
- break;
- }
- }
- octeon_set_interrupts(cpu_status_bits);
+ if ((uart_index < 0) || (uart_index > 1)) {
+ return;
+ }
+ cpu_status_bits = octeon_disable_interrupts();
+ /* Force Flush the IOBus */
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
+ for (val3 = 0xfffffffff; val3 > 0; val3--) {
+ val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
+ if (((uint8_t) val) & LSR_TEMT) {
+ break;
+ }
+ }
+ octeon_set_interrupts(cpu_status_bits);
}
@@ -447,23 +474,26 @@
* Does nothing.
* Used to mark the point for simulator to begin tracing
*/
-void octeon_debug_symbol (void)
+void
+octeon_debug_symbol(void)
{
}
-void octeon_ciu_stop_gtimer (int timer)
+void
+octeon_ciu_stop_gtimer(int timer)
{
- oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll);
+ oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll);
}
-void octeon_ciu_start_gtimer (int timer, u_int one_shot, uint64_t time_cycles)
+void
+octeon_ciu_start_gtimer(int timer, u_int one_shot, uint64_t time_cycles)
{
- octeon_ciu_gentimer gentimer;
+ octeon_ciu_gentimer gentimer;
- gentimer.word64 = 0;
- gentimer.bits.one_shot = one_shot;
- gentimer.bits.len = time_cycles - 1;
- oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64);
+ gentimer.word64 = 0;
+ gentimer.bits.one_shot = one_shot;
+ gentimer.bits.len = time_cycles - 1;
+ oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64);
}
/*
@@ -471,22 +501,23 @@
*
* Shutdown all CIU to IP2, IP3 mappings
*/
-void octeon_ciu_reset (void)
+void
+octeon_ciu_reset(void)
{
- octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0);
- octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1);
- octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2);
- octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2);
+ octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3);
- ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0);
- ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1);
- ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0);
- ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0);
+ ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1);
- ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll);
- ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll);
- ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll);
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll);
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll);
+ ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll);
}
/*
@@ -494,12 +525,13 @@
*
* Disable interrupts in the CPU controller
*/
-void mips_disable_interrupt_controls (void)
+void
+mips_disable_interrupt_controls(void)
{
- /*
- * Disable interrupts in CIU.
- */
- octeon_ciu_reset();
+ /*
+ * Disable interrupts in CIU.
+ */
+ octeon_ciu_reset();
}
static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
@@ -507,101 +539,108 @@
/*
* ciu_get_intr_sum_reg_addr
*/
-static uint64_t ciu_get_intr_sum_reg_addr (int core_num, int intx, int enx)
+static uint64_t
+ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx)
{
- uint64_t ciu_intr_sum_reg_addr;
+ uint64_t ciu_intr_sum_reg_addr;
- if (enx == CIU_EN_0) {
- ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR + (core_num * 0x10) +
- (intx * 0x8);
- } else {
- ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR;
- }
+ if (enx == CIU_EN_0) {
+ ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR + (core_num * 0x10) +
+ (intx * 0x8);
+ } else {
+ ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR;
+ }
- return (ciu_intr_sum_reg_addr);
+ return (ciu_intr_sum_reg_addr);
}
-//#ifndef OCTEON_SMP
+//
+#ifndef OCTEON_SMP
static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
/*
* ciu_get_intr_en_reg_addr
*/
-static uint64_t ciu_get_intr_en_reg_addr (int core_num, int intx, int enx)
+static uint64_t
+ciu_get_intr_en_reg_addr(int core_num, int intx, int enx)
{
- uint64_t ciu_intr_reg_addr;
+ uint64_t ciu_intr_reg_addr;
- ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + ((enx == 0) ? 0x0 : 0x8) +
- (intx * 0x10) + (core_num * 0x20);
+ ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + ((enx == 0) ? 0x0 : 0x8) +
+ (intx * 0x10) + (core_num * 0x20);
- return (ciu_intr_reg_addr);
+ return (ciu_intr_reg_addr);
}
-//#else
+//
+#else
-uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip);
+uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
/*
* ciu_get_intr_reg_addr
*
* 200 ---int0,en0 ip2
* 208 ---int0,en1 ip2 ----> this is wrong... this is watchdog
- *
+ *
* 210 ---int0,en0 ip3 --
* 218 ---int0,en1 ip3 ----> same here.. .this is watchdog... right?
- *
+ *
* 220 ---int1,en0 ip2
* 228 ---int1,en1 ip2
* 230 ---int1,en0 ip3 --
* 238 ---int1,en1 ip3
*
*/
-uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip)
+uint64_t
+ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip)
{
- uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
+ uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
- if (enx < CIU_EN_0 || enx > CIU_EN_1) {
- printf("%s: invalid enx value %d, should be %d or %d\n",
- __FUNCTION__, enx, CIU_EN_0, CIU_EN_1);
- return 0;
- }
- if (intx < CIU_INT_0 || intx > CIU_INT_1) {
- printf("%s: invalid intx value %d, should be %d or %d\n",
- __FUNCTION__, enx, CIU_INT_0, CIU_INT_1);
- return 0;
- }
- if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
- printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
- __FUNCTION__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
- return 0;
- }
+ if (enx < CIU_EN_0 || enx > CIU_EN_1) {
+ printf("%s: invalid enx value %d, should be %d or %d\n",
+ __FUNCTION__, enx, CIU_EN_0, CIU_EN_1);
+ return 0;
+ }
+ if (intx < CIU_INT_0 || intx > CIU_INT_1) {
+ printf("%s: invalid intx value %d, should be %d or %d\n",
+ __FUNCTION__, enx, CIU_INT_0, CIU_INT_1);
+ return 0;
+ }
+ if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
+ printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
+ __FUNCTION__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
+ return 0;
+ }
+ ciu_intr_reg_addr += (enx * 0x8);
+ ciu_intr_reg_addr += (ciu_ip * 0x10);
+ ciu_intr_reg_addr += (intx * 0x20);
- ciu_intr_reg_addr += (enx * 0x8);
- ciu_intr_reg_addr += (ciu_ip * 0x10);
- ciu_intr_reg_addr += (intx * 0x20);
+ return (ciu_intr_reg_addr);
+}
- return (ciu_intr_reg_addr);
-}
-//#endif
+//
+#endif
/*
* ciu_get_int_summary
*/
-uint64_t ciu_get_int_summary (int core_num, int intx, int enx)
+uint64_t ciu_get_int_summary(int core_num, int intx, int enx)
{
- uint64_t ciu_intr_sum_reg_addr;
+ uint64_t ciu_intr_sum_reg_addr;
- if (core_num == CIU_THIS_CORE) {
- core_num = octeon_get_core_num();
- }
- ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
- return (oct_read64(ciu_intr_sum_reg_addr));
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
+ ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
+ return (oct_read64(ciu_intr_sum_reg_addr));
}
-//#define DEBUG_CIU 1
+//
+#define DEBUG_CIU 1
#ifdef DEBUG_CIU
#define DEBUG_CIU_SUM 1
@@ -612,121 +651,122 @@
/*
* ciu_clear_int_summary
*/
-void ciu_clear_int_summary (int core_num, int intx, int enx, uint64_t write_bits)
+void
+ciu_clear_int_summary(int core_num, int intx, int enx, uint64_t write_bits)
{
- uint32_t cpu_status_bits;
- uint64_t ciu_intr_sum_reg_addr;
+ uint32_t cpu_status_bits;
+ uint64_t ciu_intr_sum_reg_addr;
-//#define DEBUG_CIU_SUM 1
+ //
+#define DEBUG_CIU_SUM 1
#ifdef DEBUG_CIU_SUM
- uint64_t ciu_intr_sum_bits;
+ uint64_t ciu_intr_sum_bits;
#endif
- if (core_num == CIU_THIS_CORE) {
- core_num = octeon_get_core_num();
- }
-
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
#ifdef DEBUG_CIU_SUM
- printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
- core_num, intx, enx, write_bits);
+ printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
+ core_num, intx, enx, write_bits);
#endif
- cpu_status_bits = octeon_disable_interrupts();
+ cpu_status_bits = octeon_disable_interrupts();
- ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
+ ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
#ifdef DEBUG_CIU_SUM
- ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
- printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
- cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
- ciu_intr_sum_bits | write_bits);
+ ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
+ printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
+ cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
+ ciu_intr_sum_bits | write_bits);
#endif
- oct_write64(ciu_intr_sum_reg_addr, write_bits);
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
+ oct_write64(ciu_intr_sum_reg_addr, write_bits);
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
#ifdef DEBUG_CIU_SUM
- printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
+ printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
#endif
-
- octeon_set_interrupts(cpu_status_bits);
+
+ octeon_set_interrupts(cpu_status_bits);
}
/*
* ciu_disable_intr
*/
-void ciu_disable_intr (int core_num, int intx, int enx)
+void
+ciu_disable_intr(int core_num, int intx, int enx)
{
- uint32_t cpu_status_bits;
- uint64_t ciu_intr_reg_addr;
+ uint32_t cpu_status_bits;
+ uint64_t ciu_intr_reg_addr;
- if (core_num == CIU_THIS_CORE) {
- core_num = octeon_get_core_num();
- }
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
+ cpu_status_bits = octeon_disable_interrupts();
- cpu_status_bits = octeon_disable_interrupts();
-
- ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
+ ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
- oct_read64(ciu_intr_reg_addr); /* Dummy read */
+ oct_read64(ciu_intr_reg_addr); /* Dummy read */
- oct_write64(ciu_intr_reg_addr, 0LL);
- oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
+ oct_write64(ciu_intr_reg_addr, 0LL);
+ oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
- octeon_set_interrupts(cpu_status_bits);
+ octeon_set_interrupts(cpu_status_bits);
}
-void ciu_dump_interrutps_enabled (int core_num, int intx, int enx, int ciu_ip);
-void ciu_dump_interrutps_enabled (int core_num, int intx, int enx, int ciu_ip)
+void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
+void
+ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip)
{
uint64_t ciu_intr_reg_addr;
uint64_t ciu_intr_bits;
- if (core_num == CIU_THIS_CORE) {
- core_num = octeon_get_core_num();
- }
-
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
#ifndef OCTEON_SMP_1
ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
#else
ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
#endif
- if (!ciu_intr_reg_addr) {
- printf("Bad call to %s\n", __FUNCTION__);
- while(1);
- return;
- }
-
- ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
- printf(" CIU core %d int: %d en: %d ip: %d Add: 0x%llX enabled: 0x%llX SR: %X\n",
- core_num, intx, enx, ciu_ip, ciu_intr_reg_addr, ciu_intr_bits, mips_rd_status());
+ if (!ciu_intr_reg_addr) {
+ printf("Bad call to %s\n", __FUNCTION__);
+ while (1);
+ return;
+ }
+ ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
+ printf(" CIU core %d int: %d en: %d ip: %d Add: 0x%llX enabled: 0x%llX SR: %X\n",
+ core_num, intx, enx, ciu_ip, ciu_intr_reg_addr, ciu_intr_bits, mips_rd_status());
}
/*
* ciu_enable_interrupts
*/
-void ciu_enable_interrupts (int core_num, int intx, int enx, uint64_t set_these_interrupt_bits,
- int ciu_ip)
+void
+ciu_enable_interrupts(int core_num, int intx, int enx, uint64_t set_these_interrupt_bits,
+ int ciu_ip)
{
uint32_t cpu_status_bits;
uint64_t ciu_intr_reg_addr;
uint64_t ciu_intr_bits;
- if (core_num == CIU_THIS_CORE) {
- core_num = octeon_get_core_num();
- }
+ if (core_num == CIU_THIS_CORE) {
+ core_num = octeon_get_core_num();
+ }
+ //
+#define DEBUG_CIU_EN 1
-// #define DEBUG_CIU_EN 1
-
#ifdef DEBUG_CIU_EN
- printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
- core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
+ printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
+ core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
#endif
cpu_status_bits = octeon_disable_interrupts();
@@ -737,19 +777,18 @@
ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
#endif
- if (!ciu_intr_reg_addr) {
- printf("Bad call to %s\n", __FUNCTION__);
- while(1);
- return;
- }
-
- ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
+ if (!ciu_intr_reg_addr) {
+ printf("Bad call to %s\n", __FUNCTION__);
+ while (1);
+ return;
+ }
+ ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
#ifdef DEBUG_CIU_EN
- printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
- cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
+ printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
+ cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
#endif
- ciu_intr_bits |= set_these_interrupt_bits;
+ ciu_intr_bits |= set_these_interrupt_bits;
oct_write64(ciu_intr_reg_addr, ciu_intr_bits);
#ifdef OCTEON_SMP
mips_wbflush();
@@ -757,7 +796,7 @@
oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
#ifdef DEBUG_CIU_EN
- printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_reg_addr));
+ printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_reg_addr));
#endif
octeon_set_interrupts(cpu_status_bits);
@@ -765,10 +804,10 @@
static void
-mips_platform_init (void)
+mips_platform_init(void)
{
- octeon_ciu_reset();
- octeon_uart_write_string(0, "\nPlatform Starting\n");
+ octeon_ciu_reset();
+ octeon_uart_write_string(0, "\nPlatform Starting\n");
}
@@ -781,7 +820,7 @@
****************************************************************************************
*/
-/* Define the struct that is initialized by the bootloader used by the
+/* Define the struct that is initialized by the bootloader used by the
* startup code.
*
* Copyright (c) 2004, 2005, 2006 Cavium Networks.
@@ -803,89 +842,94 @@
typedef struct {
- /* Start of block referenced by assembly code - do not change! */
- uint32_t desc_version;
- uint32_t desc_size;
+ /* Start of block referenced by assembly code - do not change! */
+ uint32_t desc_version;
+ uint32_t desc_size;
- uint64_t stack_top;
- uint64_t heap_base;
- uint64_t heap_end;
- uint64_t entry_point; /* Only used by bootloader */
- uint64_t desc_vaddr;
- /* End of This block referenced by assembly code - do not change! */
+ uint64_t stack_top;
+ uint64_t heap_base;
+ uint64_t heap_end;
+ uint64_t entry_point; /* Only used by bootloader */
+ uint64_t desc_vaddr;
+ /* End of This block referenced by assembly code - do not change! */
- uint32_t exception_base_addr;
- uint32_t stack_size;
- uint32_t heap_size;
- uint32_t argc; /* Argc count for application */
- uint32_t argv[OCTEON_ARGV_MAX_ARGS];
- uint32_t flags;
- uint32_t core_mask;
- uint32_t dram_size; /**< DRAM size in megabyes */
- uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
- uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
- uint32_t eclock_hz; /**< CPU clock speed, in hz */
- uint32_t dclock_hz; /**< DRAM clock speed, in hz */
- uint32_t spi_clock_hz; /**< SPI4 clock in hz */
- uint16_t board_type;
- uint8_t board_rev_major;
- uint8_t board_rev_minor;
- uint16_t chip_type;
- uint8_t chip_rev_major;
- uint8_t chip_rev_minor;
- char board_serial_number[OCTEON_SERIAL_LEN];
- uint8_t mac_addr_base[6];
- uint8_t mac_addr_count;
- uint64_t cvmx_desc_vaddr;
+ uint32_t exception_base_addr;
+ uint32_t stack_size;
+ uint32_t heap_size;
+ uint32_t argc; /* Argc count for application */
+ uint32_t argv[OCTEON_ARGV_MAX_ARGS];
+ uint32_t flags;
+ uint32_t core_mask;
+ uint32_t dram_size; /**< DRAM size in megabyes */
+ uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
+ uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
+ uint32_t eclock_hz; /**< CPU clock speed, in hz */
+ uint32_t dclock_hz; /**< DRAM clock speed, in hz */
+ uint32_t spi_clock_hz; /**< SPI4 clock in hz */
+ uint16_t board_type;
+ uint8_t board_rev_major;
+ uint8_t board_rev_minor;
+ uint16_t chip_type;
+ uint8_t chip_rev_major;
+ uint8_t chip_rev_minor;
+ char board_serial_number[OCTEON_SERIAL_LEN];
+ uint8_t mac_addr_base[6];
+ uint8_t mac_addr_count;
+ uint64_t cvmx_desc_vaddr;
-} octeon_boot_descriptor_t;
+} octeon_boot_descriptor_t;
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 2
typedef struct {
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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