PERFORCE change 134690 for review
Olivier Houchard
cognet at FreeBSD.org
Sat Feb 2 18:38:01 PST 2008
http://perforce.freebsd.org/chv.cgi?CH=134690
Change 134690 by cognet at cognet-mips on 2008/02/03 02:37:32
Make sure SR_KX is preserved in context switches. I didn't make it
conditional on TARGET_OCTEON, I think it won't hurt.
As the Cavium port does, allocate 3 pages for the kstack, and if
td_kstack is not 8kB aligned, use td_kstack + 4kB instead. This is
not optimal, but this way, we do not have to touch MI bits in sys/vm.
I thought we had another solution, if I did something stupid, feel
free to backout those bits (but be sure to keep the SR_KX ones).
Affected files ...
.. //depot/projects/mips2-jnpr/src/sys/mips/include/param.h#7 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/include/proc.h#5 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#11 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/genassym.c#5 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#22 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/nexus.c#4 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/pmap.c#18 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#10 edit
.. //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#13 edit
Differences ...
==== //depot/projects/mips2-jnpr/src/sys/mips/include/param.h#7 (text+ko) ====
@@ -124,7 +124,7 @@
* Therefore, any code imported from OpenBSD which depends on
* UADDR, UVPN and KERNELSTACK requires porting.
*/
-#define KSTACK_PAGES 2 /* kernel stack*/
+#define KSTACK_PAGES 3 /* kernel stack*/
#define KSTACK_GUARD_PAGES 0 /* pages of kstack guard; 0 disables */
#define UPAGES 2
==== //depot/projects/mips2-jnpr/src/sys/mips/include/proc.h#5 (text+ko) ====
@@ -53,6 +53,7 @@
int md_pc_ctrl; /* performance counter control */
int md_pc_count; /* performance counter */
int md_pc_spill; /* performance counter spill */
+ vm_offset_t md_realstack;
};
/* md_flags */
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#11 (text+ko) ====
@@ -1041,7 +1041,7 @@
sys_stk_chk:
GET_CPU_PCPU(k0)
lw k0, PC_CURTHREAD(k0)
- lw k0, TD_KSTACK(k0)
+ lw k0, TD_REALKSTACK(k0)
sltu k0, sp, k0 # check for stack overflow
beqz k0, _C_LABEL(MipsKernGenException) # not stack overflow
nop
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/genassym.c#5 (text+ko) ====
@@ -65,7 +65,7 @@
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_UPTE, offsetof(struct thread, td_md.md_upte));
-ASSYM(TD_KSTACK, offsetof(struct thread, td_kstack));
+ASSYM(TD_REALKSTACK, offsetof(struct thread, td_md.md_realstack));
ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#22 (text+ko) ====
@@ -265,6 +265,10 @@
proc_linkup(&proc0, &thread0);
thread0.td_kstack = kstack0;
thread0.td_kstack_pages = KSTACK_PAGES;
+ if (thread0.td_kstack & (1 << PAGE_SHIFT))
+ thread0.td_md.md_realstack = thread0.td_kstack + PAGE_SIZE;
+ else
+ thread0.td_md.md_realstack = thread0.td_kstack;
/* Initialize pcpu info of cpu-zero */
#ifdef SMP
pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
@@ -276,8 +280,8 @@
* thread0 is the only thread that has kstack located in KSEG0
* while cpu_thread_alloc handles kstack allocated in KSEG2.
*/
- thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
- thread0.td_kstack_pages * PAGE_SIZE) - 1;
+ thread0.td_pcb = (struct pcb *)(thread0.td_md.md_realstack +
+ (thread0.td_kstack_pages - 1) * PAGE_SIZE) - 1;
thread0.td_frame = &thread0.td_pcb->pcb_regs;
/*
* There is no need to initialize md_upte array for thread0 as it's
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/nexus.c#4 (text+ko) ====
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/pmap.c#18 (text+ko) ====
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#10 (text+ko) ====
@@ -263,7 +263,9 @@
mfc0 t0, COP_0_STATUS_REG # t0 = saved status register
nop
nop
- mtc0 zero, COP_0_STATUS_REG # Disable all interrupts
+
+ and a3, t0, SR_KX
+ mtc0 a3, COP_0_STATUS_REG # Disable all interrupts
ITLBNOPFIX
j mips_sw1 # We're not interested in old
# thread's context, so jump
@@ -281,7 +283,8 @@
mfc0 t0, COP_0_STATUS_REG # t0 = saved status register
nop
nop
- mtc0 zero, COP_0_STATUS_REG # Disable all interrupts
+ and a3, t0, SR_KX
+ mtc0 a3, COP_0_STATUS_REG # Disable all interrupts
ITLBNOPFIX
beqz a0, mips_sw1
move a3, a0
@@ -326,7 +329,7 @@
sw a1, PC_CURTHREAD(a3)
lw a2, TD_PCB(a1)
sw a2, PC_CURPCB(a3)
- lw v0, TD_KSTACK(a1)
+ lw v0, TD_REALKSTACK(a1)
li s0, (MIPS_KSEG2_START+VM_KERNEL_ALLOC_OFFSET) # If Uarea addr is below kseg2,
bltu v0, s0, sw2 # no need to insert in TLB.
lw a1, TD_UPTE+0(s7) # t0 = first u. pte
==== //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#13 (text+ko) ====
@@ -114,10 +114,13 @@
if ((flags & RFPROC) == 0)
return;
-
+ if(td2->td_kstack & (1 << PAGE_SHIFT))
+ td2->td_md.md_realstack = td2->td_kstack + PAGE_SIZE;
+ else
+ td2->td_md.md_realstack = td2->td_kstack;
/* Point the pcb to the top of the stack */
- pcb2 = (struct pcb *)(td2->td_kstack +
- td2->td_kstack_pages * PAGE_SIZE) - 1;
+ pcb2 = (struct pcb *)(td2->td_md.md_realstack +
+ (td2->td_kstack_pages - 1) * PAGE_SIZE) - 1;
td2->td_pcb = pcb2;
/* Copy p1's pcb */
@@ -248,8 +251,13 @@
pt_entry_t *pte;
int i;
- td->td_pcb = (struct pcb *)(td->td_kstack +
- td->td_kstack_pages * PAGE_SIZE) - 1;
+ if(td->td_kstack & (1 << PAGE_SHIFT))
+ td->td_md.md_realstack = td->td_kstack + PAGE_SIZE;
+ else
+ td->td_md.md_realstack = td->td_kstack;
+
+ td->td_pcb = (struct pcb *)(td->td_md.md_realstack +
+ (td->td_kstack_pages - 1) * PAGE_SIZE) - 1;
td->td_frame = &td->td_pcb->pcb_regs;
if (!(pte = pmap_segmap(kernel_pmap, (vm_offset_t)td->td_kstack)))
More information about the p4-projects
mailing list