PERFORCE change 148410 for review
Marius Strobl
marius at FreeBSD.org
Mon Aug 25 18:14:25 UTC 2008
http://perforce.freebsd.org/chv.cgi?CH=148410
Change 148410 by marius at flak on 2008/08/25 18:13:40
- Announce the speed of the PCI bus for informational purpose.
- Schizo revision >= 2.3 also require manual DMA sync.
- Rename macros in order to take the XMITS PCI-X host-PCI-bridges,
which should be also handled by this driver, into account. Due
to lack of such hardware that's it for now though.
Affected files ...
.. //depot/projects/usiii/sparc64/pci/schizo.c#10 edit
.. //depot/projects/usiii/sparc64/pci/schizoreg.h#4 edit
.. //depot/projects/usiii/sparc64/pci/schizovar.h#4 edit
Differences ...
==== //depot/projects/usiii/sparc64/pci/schizo.c#10 (text+ko) ====
@@ -35,7 +35,8 @@
__FBSDID("$FreeBSD$");
/*
- * Support for `Schizo' Safari to PCI and `Tomatillo' JBus to PCI bridges
+ * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
+ * PCI 2.2 bridges
*/
#include "opt_ofw_pci.h"
@@ -174,32 +175,33 @@
driver_filter_t *sds_handler;
void *sds_arg;
void *sds_cookie;
+ uint64_t sds_syncreg;
u_int sds_ino;
};
-#define SCZTOM_PERF_CNT_QLTY 100
+#define SCHIZO_PERF_CNT_QLTY 100
-#define SCZTOM_SPC_READ_8(spc, sc, offs) \
+#define SCHIZO_SPC_READ_8(spc, sc, offs) \
bus_read_8((sc)->sc_mem_res[(spc)], (offs))
-#define SCZTOM_SPC_WRITE_8(spc, sc, offs, v) \
+#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
-#define SCZTOM_PCI_READ_8(sc, offs) \
- SCZTOM_SPC_READ_8(SCZTOM_PCI, (sc), (offs))
-#define SCZTOM_PCI_WRITE_8(sc, offs, v) \
- SCZTOM_SPC_WRITE_8(SCZTOM_PCI, (sc), (offs), (v))
-#define SCZTOM_CTRL_READ_8(sc, offs) \
- SCZTOM_SPC_READ_8(SCZTOM_CTRL, (sc), (offs))
-#define SCZTOM_CTRL_WRITE_8(sc, offs, v) \
- SCZTOM_SPC_WRITE_8(SCZTOM_CTRL, (sc), (offs), (v))
-#define SCZTOM_PCICFG_READ_8(sc, offs) \
- SCZTOM_SPC_READ_8(SCZTOM_PCICFG, (sc), (offs))
-#define SCZTOM_PCICFG_WRITE_8(sc, offs, v) \
- SCZTOM_SPC_WRITE_8(SCZTOM_PCICFG, (sc), (offs), (v))
-#define SCZTOM_ICON_READ_8(sc, offs) \
- SCZTOM_SPC_READ_8(SCZTOM_ICON, (sc), (offs))
-#define SCZTOM_ICON_WRITE_8(sc, offs, v) \
- SCZTOM_SPC_WRITE_8(SCZTOM_ICON, (sc), (offs), (v))
+#define SCHIZO_PCI_READ_8(sc, offs) \
+ SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
+#define SCHIZO_PCI_WRITE_8(sc, offs, v) \
+ SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
+#define SCHIZO_CTRL_READ_8(sc, offs) \
+ SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
+#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
+ SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
+#define SCHIZO_PCICFG_READ_8(sc, offs) \
+ SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
+#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
+ SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
+#define SCHIZO_ICON_READ_8(sc, offs) \
+ SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
+#define SCHIZO_ICON_WRITE_8(sc, offs, v) \
+ SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
#define OFW_PCI_TYPE "pci"
@@ -282,17 +284,17 @@
* (2) per-PBM PCI configuration space
* (3) per-PBM interrupt concentrator registers
*/
- sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY,
- SCZTOM_PCI) >> 20) & 1;
+ sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
+ 20) & 1;
for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
n++) {
rid = n;
sc->sc_mem_res[n] = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid,
(((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
- n == SCZTOM_PCI) || n == SCZTOM_CTRL)) ||
+ n == STX_PCI) || n == STX_CTRL)) ||
(mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
- n == SCZTOM_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
+ n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
if (sc->sc_mem_res[n] == NULL)
panic("%s: could not allocate register bank %d",
__func__, n);
@@ -305,8 +307,8 @@
*/
osc = NULL;
SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
- if (rman_get_start(asc->sc_mem_res[SCZTOM_CTRL]) ==
- rman_get_start(sc->sc_mem_res[SCZTOM_CTRL])) {
+ if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
+ rman_get_start(sc->sc_mem_res[STX_CTRL])) {
/* Found partner. */
osc = asc;
break;
@@ -328,59 +330,62 @@
panic("%s: could not determine IGN", __func__);
if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1)
panic("%s: could not determine version", __func__);
+ if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
+ prop = 33000000;
- device_printf(dev, "%s, version %d, IGN %#x, bus %c\n",
- desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half);
+ device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n",
+ desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half,
+ prop / 1000 / 1000);
/* Set up the PCI interrupt retry timer. */
#ifdef SCHIZO_DEBUG
device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long)
- SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_INTR_RETRY_TIM));
+ SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM));
#endif
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_INTR_RETRY_TIM, 5);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5);
/* Set up the PCI control register. */
- reg = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_CTRL);
- reg |= SCZTOM_PCI_CTRL_MMU_IEN | SCZTOM_PCI_CTRL_SBH_IEN |
- SCZTOM_PCI_CTRL_ERR_IEN | SCZTOM_PCI_CTRL_ARB_MASK;
- reg &= ~(TOM_PCI_CTRL_DTO_IEN | SCZTOM_PCI_CTRL_SERR |
- SCZTOM_PCI_CTRL_ARB_PARK);
+ reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
+ reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
+ STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK;
+ reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_SERR |
+ STX_PCI_CTRL_ARB_PARK);
if (OF_getproplen(node, "no-bus-parking") < 0)
- reg |= SCZTOM_PCI_CTRL_ARB_PARK;
+ reg |= STX_PCI_CTRL_ARB_PARK;
if (mode == SCHIZO_MODE_TOM) {
reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
if (sc->sc_ver <= 1)
reg |= TOM_PCI_CTRL_DTO_IEN;
else
- reg |= SCZTOM_PCI_CTRL_PTO;
+ reg |= STX_PCI_CTRL_PTO;
}
#ifdef SCHIZO_DEBUG
device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
- (unsigned long long)SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_CTRL),
+ (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL),
(unsigned long long)reg);
#endif
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_CTRL, reg);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg);
/* Clear PCI AFSR. */
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_AFSR, SCZTOM_PCI_AFSR_ERRMASK);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, STX_PCI_AFSR_ERRMASK);
/* Set up the PCI diagnostic register. */
- reg = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_DIAG);
- reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | SCZTOM_PCI_DIAG_RETRY_DIS |
- SCZTOM_PCI_DIAG_INTRSYNC_DIS);
+ reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
+ reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
+ STX_PCI_DIAG_INTRSYNC_DIS);
#ifdef SCHIZO_DEBUG
device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
- (unsigned long long)SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_DIAG),
+ (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
(unsigned long long)reg);
#endif
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_DIAG, reg);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
/*
* On Tomatillo clear the I/O prefetch lengths (workaround for a
* Jalapeno bug).
*/
if (mode == SCHIZO_MODE_TOM)
- SCZTOM_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
+ SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
(1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
@@ -395,10 +400,10 @@
if (n == -1)
panic("%s: could not get ino-bitmap", __func__);
reg = ((uint64_t)prop_array[1] << 32) | prop_array[0];
- for (n = 0; n <= SCZTOM_MAX_INO; n++) {
+ for (n = 0; n <= STX_MAX_INO; n++) {
if ((reg & (1ULL << n)) == 0)
continue;
- if (n == SCZTOM_FB0_INO || n == SCZTOM_FB1_INO)
+ if (n == STX_FB0_INO || n == STX_FB1_INO)
/* Leave for upa(4). */
continue;
if (schizo_get_intrmap(sc, n, &intrmap, &intrclr) == 0)
@@ -412,7 +417,7 @@
sica->sica_clr = intrclr;
#ifdef SCHIZO_DEBUG
device_printf(dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
- n, (u_long)intrmap, (u_long)SCZTOM_PCI_READ_8(sc, intrmap),
+ n, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
(u_long)intrclr);
#endif
if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
@@ -429,9 +434,9 @@
* the latter as the argument for the interrupt controller.
*/
if (sc->sc_half == 0) {
- if ((reg & (1ULL << SCZTOM_PCIERR_A_INO)) != 0 ||
+ if ((reg & (1ULL << STX_PCIERR_A_INO)) != 0 ||
(osc != NULL && ((struct schizo_icarg *)intr_vectors[
- INTMAP_VEC(sc->sc_ign, SCZTOM_PCIERR_A_INO)].iv_icarg)->
+ INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
sica_sc == osc))
/*
* We are the driver for PBM A and either also
@@ -439,21 +444,21 @@
* the driver for PBM B has probed first and
* registered it for us.
*/
- schizo_set_intr(sc, 0, SCZTOM_PCIERR_A_INO,
+ schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
schizo_pci_bus);
- if ((reg & (1ULL << SCZTOM_PCIERR_B_INO)) != 0 && osc != NULL)
+ if ((reg & (1ULL << STX_PCIERR_B_INO)) != 0 && osc != NULL)
/*
* We are the driver for PBM A but registered
* the interrupt controller for PBM B, i.e. the
* driver for PBM B attached first but couldn't
* set up a handler for PBM B.
*/
- schizo_set_intr(osc, 0, SCZTOM_PCIERR_B_INO,
+ schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
schizo_pci_bus);
} else {
- if ((reg & (1ULL << SCZTOM_PCIERR_B_INO)) != 0 ||
+ if ((reg & (1ULL << STX_PCIERR_B_INO)) != 0 ||
(osc != NULL && ((struct schizo_icarg *)intr_vectors[
- INTMAP_VEC(sc->sc_ign, SCZTOM_PCIERR_B_INO)].iv_icarg)->
+ INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
sica_sc == osc))
/*
* We are the driver for PBM B and either also
@@ -461,24 +466,24 @@
* the driver for PBM A has probed first and
* registered it for us.
*/
- schizo_set_intr(sc, 0, SCZTOM_PCIERR_B_INO,
+ schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
schizo_pci_bus);
- if ((reg & (1ULL << SCZTOM_PCIERR_A_INO)) != 0 && osc != NULL)
+ if ((reg & (1ULL << STX_PCIERR_A_INO)) != 0 && osc != NULL)
/*
* We are the driver for PBM B but registered
* the interrupt controller for PBM A, i.e. the
* driver for PBM A attached first but couldn't
* set up a handler for PBM A.
*/
- schizo_set_intr(osc, 0, SCZTOM_PCIERR_A_INO,
+ schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
schizo_pci_bus);
}
- if ((reg & (1ULL << SCZTOM_UE_INO)) != 0)
- schizo_set_intr(sc, 1, SCZTOM_UE_INO, schizo_ue);
- if ((reg & (1ULL << SCZTOM_CE_INO)) != 0)
- schizo_set_intr(sc, 2, SCZTOM_CE_INO, schizo_ce);
- if ((reg & (1ULL << SCZTOM_BUS_INO)) != 0)
- schizo_set_intr(sc, 3, SCZTOM_BUS_INO, schizo_host_bus);
+ if ((reg & (1ULL << STX_UE_INO)) != 0)
+ schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
+ if ((reg & (1ULL << STX_CE_INO)) != 0)
+ schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
+ if ((reg & (1ULL << STX_BUS_INO)) != 0)
+ schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
/*
* Setup Safari/JBus performance counter 0 in bus cycle counting
@@ -490,15 +495,15 @@
* "pair" of Tomatillos, too.
*/
if (sc->sc_half == 0) {
- SCZTOM_CTRL_WRITE_8(sc, SCZTOM_CTRL_PERF,
- (SCZTOM_CTRL_PERF_DIS << SCZTOM_CTRL_PERF_CNT1_SHIFT) |
- (SCZTOM_CTRL_PERF_BUSCYC << SCZTOM_CTRL_PERF_CNT0_SHIFT));
+ SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF,
+ (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
+ (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
if (tc == NULL)
panic("%s: could not malloc timecounter", __func__);
tc->tc_get_timecount = schizo_get_timecount;
tc->tc_poll_pps = NULL;
- tc->tc_counter_mask = SCZTOM_CTRL_PERF_CNT_MASK;
+ tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
sizeof(prop)) == -1)
panic("%s: could not determine clock frequency",
@@ -506,19 +511,19 @@
tc->tc_frequency = prop;
tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
if (mode == SCHIZO_MODE_SCZ)
- tc->tc_quality = SCZTOM_PERF_CNT_QLTY;
+ tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
else
- tc->tc_quality = -SCZTOM_PERF_CNT_QLTY;
+ tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
tc->tc_priv = sc;
tc_init(tc);
}
/* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */
- sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(SCZTOM_IOMMU_BITS);
+ sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
sc->sc_is.is_sb[0] = 0;
sc->sc_is.is_sb[1] = 0;
if (OF_getproplen(node, "no-streaming-cache") < 0)
- sc->sc_is.is_sb[0] = SCZTOM_PCI_STRBUF;
+ sc->sc_is.is_sb[0] = STX_PCI_STRBUF;
#define TSBCASE(x) \
case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
@@ -552,12 +557,12 @@
sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
if (rman_init(&sc->sc_pci_io_rman) != 0 ||
- rman_manage_region(&sc->sc_pci_io_rman, 0, SCZTOM_IO_SIZE) != 0)
+ rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
panic("%s: failed to set up I/O rman", __func__);
sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
- rman_manage_region(&sc->sc_pci_mem_rman, 0, SCZTOM_MEM_SIZE) != 0)
+ rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
panic("%s: failed to set up memory rman", __func__);
nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
@@ -566,7 +571,7 @@
* Make sure that the expected ranges are present. The
* OFW_PCI_CS_MEM64 one is not currently used though.
*/
- if (nrange != SCZTOM_NRANGE)
+ if (nrange != STX_NRANGE)
panic("%s: unsupported number of ranges", __func__);
/*
* Find the addresses of the various bus spaces.
@@ -574,7 +579,7 @@
* The physical start addresses of the ranges are the configuration,
* memory and I/O handles.
*/
- for (n = 0; n < SCZTOM_NRANGE; n++) {
+ for (n = 0; n < STX_NRANGE; n++) {
i = OFW_PCI_RANGE_CS(&range[n]);
if (sc->sc_pci_bh[i] != 0)
panic("%s: duplicate range for space %d", __func__, i);
@@ -613,17 +618,17 @@
sc->sc_pci_secbus = prop_array[0];
/* Clear PCI status error bits. */
- PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, SCZTOM_CS_DEVICE,
- SCZTOM_CS_FUNC, PCIR_STATUS, PCIM_STATUS_PERR |
- PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
+ PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
+ PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT |
+ PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
PCIM_STATUS_PERRREPORT, 2);
/*
* Set the latency timer register as this isn't always done by the
* firmware.
*/
- PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, SCZTOM_CS_DEVICE,
- SCZTOM_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
+ PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
+ PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
@@ -663,15 +668,15 @@
* on that PCI controller.
*/
- if (ino > SCZTOM_MAX_INO) {
+ if (ino > STX_MAX_INO) {
device_printf(sc->sc_dev, "out of range INO %d requested\n",
ino);
return (0);
}
- intrmap = SCZTOM_PCI_IMAP_BASE + (ino << 3);
- intrclr = SCZTOM_PCI_ICLR_BASE + (ino << 3);
- mr = SCZTOM_PCI_READ_8(sc, intrmap);
+ intrmap = STX_PCI_IMAP_BASE + (ino << 3);
+ intrclr = STX_PCI_ICLR_BASE + (ino << 3);
+ mr = SCHIZO_PCI_READ_8(sc, intrmap);
if (INTINO(mr) != ino) {
device_printf(sc->sc_dev,
"interrupt map entry does not match INO (%d != %d)\n",
@@ -696,13 +701,13 @@
uint64_t afar, afsr, csr, iommu;
uint32_t status;
- afar = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_AFAR);
- afsr = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_AFSR);
- csr = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_CTRL);
- iommu = SCZTOM_PCI_READ_8(sc, SCZTOM_PCI_IOMMU);
+ afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
+ afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
+ csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
+ iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
- SCZTOM_CS_DEVICE, SCZTOM_CS_FUNC, PCIR_STATUS, 2);
- if ((csr & SCZTOM_PCI_CTRL_MMU_ERR) != 0) {
+ STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
+ if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) {
if ((iommu & TOM_PCI_IOMMU_ERR) == 0)
goto clear_error;
@@ -712,7 +717,7 @@
TOM_PCI_IOMMU_INVALID_ERR ||
(iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 ||
(iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) {
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_IOMMU, iommu);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
goto clear_error;
}
}
@@ -731,10 +736,10 @@
(unsigned long long)afar, (unsigned long long)afsr,
(unsigned long long)csr, (unsigned long long)status);
/* Clear the error bits that we caught. */
- PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, SCZTOM_CS_DEVICE,
- SCZTOM_CS_FUNC, PCIR_STATUS, status, 2);
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_CTRL, csr);
- SCZTOM_PCI_WRITE_8(sc, SCZTOM_PCI_AFSR, afsr);
+ PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
+ STX_CS_FUNC, PCIR_STATUS, status, 2);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
+ SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
return (FILTER_HANDLED);
}
@@ -746,10 +751,10 @@
int i;
mtx_lock_spin(sc->sc_mtx);
- afar = SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_UE_AFAR);
+ afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
for (i = 0; i < 1000; i++)
- if (((afsr = SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_UE_AFSR)) &
- SCZTOM_CTRL_CE_AFSR_ERRPNDG) == 0)
+ if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
+ STX_CTRL_CE_AFSR_ERRPNDG) == 0)
break;
mtx_unlock_spin(sc->sc_mtx);
panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
@@ -766,17 +771,17 @@
int i;
mtx_lock_spin(sc->sc_mtx);
- afar = SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_CE_AFAR);
+ afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
for (i = 0; i < 1000; i++)
- if (((afsr = SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_UE_AFSR)) &
- SCZTOM_CTRL_CE_AFSR_ERRPNDG) == 0)
+ if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
+ STX_CTRL_CE_AFSR_ERRPNDG) == 0)
break;
device_printf(sc->sc_dev,
"correctable DMA error AFAR %#llx AFSR %#llx\n",
(unsigned long long)afar, (unsigned long long)afsr);
/* Clear the error bits that we caught. */
- SCZTOM_CTRL_WRITE_8(sc, SCZTOM_CTRL_UE_AFSR,
- afsr & SCZTOM_CTRL_CE_AFSR_ERRMASK);
+ SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR,
+ afsr & STX_CTRL_CE_AFSR_ERRMASK);
mtx_unlock_spin(sc->sc_mtx);
return (FILTER_HANDLED);
}
@@ -787,7 +792,7 @@
struct schizo_softc *sc = arg;
uint64_t errlog;
- errlog = SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_BUS_ERRLOG);
+ errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
panic("%s: %s error %#llx", device_get_name(sc->sc_dev),
sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
(unsigned long long)errlog);
@@ -799,14 +804,14 @@
{
/* Punch in our copies. */
- sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[SCZTOM_PCI]);
- sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[SCZTOM_PCI]);
- sc->sc_is.is_iommu = SCZTOM_PCI_IOMMU;
- sc->sc_is.is_dtag = SCZTOM_PCI_IOMMU_TLB_TAG_DIAG;
- sc->sc_is.is_ddram = SCZTOM_PCI_IOMMU_TLB_DATA_DIAG;
- sc->sc_is.is_dqueue = SCZTOM_PCI_IOMMU_QUEUE_DIAG;
- sc->sc_is.is_dva = SCZTOM_PCI_IOMMU_SVADIAG;
- sc->sc_is.is_dtcmp = SCZTOM_PCI_IOMMU_TLB_CMP_DIAG;
+ sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
+ sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
+ sc->sc_is.is_iommu = STX_PCI_IOMMU;
+ sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
+ sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
+ sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
+ sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG;
+ sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize,
dvmabase, 0);
@@ -843,11 +848,11 @@
* The Schizo bridges contain a dupe of their header at 0x80.
*/
if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
- slot == SCZTOM_CS_DEVICE && func == SCZTOM_CS_FUNC &&
+ slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
reg + width > 0x80)
return (0);
- offset = SCZTOM_CONF_OFF(bus, slot, func, reg);
+ offset = STX_CONF_OFF(bus, slot, func, reg);
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
switch (width) {
case 1:
@@ -886,7 +891,7 @@
u_long offset = 0;
sc = device_get_softc(dev);
- offset = SCZTOM_CONF_OFF(bus, slot, func, reg);
+ offset = STX_CONF_OFF(bus, slot, func, reg);
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
switch (width) {
case 1:
@@ -952,16 +957,17 @@
int timeout;
reg = 1ULL << sds->sds_ino;
- SCZTOM_PCI_WRITE_8(sc, TOM_PCI_DMA_SYNC_PEND, reg);
+ SCHIZO_PCI_WRITE_8(sc, sds->sds_syncreg, reg);
timeout = 1000000;
- for (; SCZTOM_PCI_READ_8(sc, TOM_PCI_DMA_SYNC_PEND) & reg;)
+ for (; SCHIZO_PCI_READ_8(sc, sds->sds_syncreg) & reg;)
if (--timeout < 0)
panic("%s: DMA does not sync", __func__);
+
/*
- * Version <= 4 bridges additionally need a block store as a
- * workaround for a hardware bug.
+ * Tomatillo version <= 4 bridges additionally need a block
+ * store as a workaround for a hardware bug.
*/
- if (sc->sc_ver <= 4) {
+ if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) {
critical_enter();
reg = rd(fprs);
wr(fprs, reg | FPRS_FEF, 0);
@@ -980,7 +986,7 @@
struct intr_vector *iv = arg;
struct schizo_icarg *sica = iv->iv_icarg;
- SCZTOM_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
+ SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
}
@@ -990,7 +996,7 @@
struct intr_vector *iv = arg;
struct schizo_icarg *sica = iv->iv_icarg;
- SCZTOM_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
+ SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
}
static void
@@ -999,8 +1005,8 @@
struct intr_vector *iv = arg;
struct schizo_icarg *sica = iv->iv_icarg;
- SCZTOM_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
- SCZTOM_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
+ SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
+ SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
}
static void
@@ -1009,7 +1015,7 @@
struct intr_vector *iv = arg;
struct schizo_icarg *sica = iv->iv_icarg;
- SCZTOM_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0);
+ SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0);
}
static int
@@ -1035,19 +1041,23 @@
}
/*
- * Tomatillo bridges need to be manually told to sync DMA writes.
+ * Schizo revision >= 2.3 (i.e. version >= 5) and Tomatillo bridges
+ * need to be manually told to sync DMA writes.
* XXX setup of the wrapper and the contents of schizo_dmasync()
* should be moved to schizo(4)-specific bus_dma_tag_create() and
* bus_dmamap_sync() methods, respectively, once DMA tag creation
* is newbus'ified, so the wrapper isn't only applied for interrupt
* handlers but also for polling(4) callbacks.
*/
- if (sc->sc_mode == SCHIZO_MODE_TOM) {
+ if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
+ sc->sc_mode == SCHIZO_MODE_TOM) {
sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO);
if (sds == NULL)
return (ENOMEM);
sds->sds_sc = sc;
sds->sds_arg = arg;
+ sds->sds_syncreg = sc->sc_mode == SCHIZO_MODE_SCZ ?
+ SCZ_PCI_DMA_SYNC : TOMXMS_PCI_DMA_SYNC_PEND;
sds->sds_ino = INTINO(vec);
if (intr == NULL) {
sds->sds_handler = filt;
@@ -1238,7 +1248,7 @@
panic("%s: out of memory", __func__);
bt->bst_cookie = sc;
- bt->bst_parent = rman_get_bustag(sc->sc_mem_res[SCZTOM_PCI]);
+ bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
bt->bst_type = type;
return (bt);
}
@@ -1249,6 +1259,6 @@
struct schizo_softc *sc;
sc = tc->tc_priv;
- return (SCZTOM_CTRL_READ_8(sc, SCZTOM_CTRL_PERF_CNT) &
- (SCZTOM_CTRL_PERF_CNT_MASK << SCZTOM_CTRL_PERF_CNT_CNT0_SHIFT));
+ return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
+ (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT));
}
==== //depot/projects/usiii/sparc64/pci/schizoreg.h#4 (text+ko) ====
@@ -31,41 +31,41 @@
#ifndef _SPARC64_PCI_SCHIZOREG_H_
#define _SPARC64_PCI_SCHIZOREG_H_
-#define SCZTOM_NINTR 4
-#define SCZTOM_NRANGE 4
+#define STX_NINTR 4
+#define STX_NRANGE 4
#define SCZ_NREG 3
#define TOM_NREG 4
-#define SCZTOM_PCI 0
-#define SCZTOM_CTRL 1
-#define SCZTOM_PCICFG 2
-#define SCZTOM_ICON 3
+#define STX_PCI 0
+#define STX_CTRL 1
+#define STX_PCICFG 2
+#define STX_ICON 3
/* PCI configuration and status registers */
-#define SCZTOM_PCI_IOMMU 0x00200
-#define SCZTOM_PCI_IOMMU_CTXFLUSH 0x00218
-#define SCZTOM_PCI_IMAP_BASE 0x01000
-#define SCZTOM_PCI_ICLR_BASE 0x01400
-#define SCZTOM_PCI_INTR_RETRY_TIM 0x01a00
+#define STX_PCI_IOMMU 0x00200
+#define STX_PCI_IOMMU_CTXFLUSH 0x00218
+#define STX_PCI_IMAP_BASE 0x01000
+#define STX_PCI_ICLR_BASE 0x01400
+#define STX_PCI_INTR_RETRY_TIM 0x01a00
#define SCZ_PCI_DMA_SYNC 0x01a08
#define TOM_PCI_DMA_SYNC_COMP 0x01a10
-#define TOM_PCI_DMA_SYNC_PEND 0x01a18
-#define SCZTOM_PCI_CTRL 0x02000
-#define SCZTOM_PCI_AFSR 0x02010
-#define SCZTOM_PCI_AFAR 0x02018
-#define SCZTOM_PCI_DIAG 0x02020
+#define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18
+#define STX_PCI_CTRL 0x02000
+#define STX_PCI_AFSR 0x02010
+#define STX_PCI_AFAR 0x02018
+#define STX_PCI_DIAG 0x02020
#define TOM_PCI_IOC_CSR 0x02248
#define TOM_PCI_IOC_TAG 0x02290
#define TOM_PCI_IOC_DATA 0x02290
-#define SCZTOM_PCI_STRBUF 0x02800
-#define SCZTOM_PCI_STRBUF_CTXFLUSH 0x02818
-#define SCZTOM_PCI_IOMMU_SVADIAG 0x0a400
-#define SCZTOM_PCI_IOMMU_TLB_CMP_DIAG 0x0a408
-#define SCZTOM_PCI_IOMMU_QUEUE_DIAG 0x0a500
-#define SCZTOM_PCI_IOMMU_TLB_TAG_DIAG 0x0a580
-#define SCZTOM_PCI_IOMMU_TLB_DATA_DIAG 0x0a600
-#define SCZTOM_PCI_IOBIO_DIAG 0x0a808
-#define SCZTOM_PCI_STRBUF_CTXMATCH 0x10000
+#define STX_PCI_STRBUF 0x02800
+#define STX_PCI_STRBUF_CTXFLUSH 0x02818
+#define STX_PCI_IOMMU_SVADIAG 0x0a400
+#define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408
+#define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500
+#define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580
+#define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600
+#define STX_PCI_IOBIO_DIAG 0x0a808
+#define STX_PCI_STRBUF_CTXMATCH 0x10000
/* PCI IOMMU control registers */
#define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL
@@ -75,8 +75,8 @@
#define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL
#define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL
#define TOM_PCI_IOMMU_ERRMASK \
- (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \
- TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR)
+ (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \
+ TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR)
#define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL
/* PCI control/status register */
@@ -85,59 +85,58 @@
#define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL
#define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL
#define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL
-#define SCZTOM_PCI_CTRL_TTO_ERR 0x0000004000000000ULL
-#define SCZTOM_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL
-#define SCZTOM_PCI_CTRL_MMU_ERR 0x0000001000000000ULL
+#define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL
+#define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL
+#define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL
#define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL
-#define SCZTOM_PCI_CTRL_SERR 0x0000000400000000ULL
+#define STX_PCI_CTRL_SERR 0x0000000400000000ULL
#define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL
#define TOM_PCI_CTRL_PRM 0x0000000040000000ULL
#define TOM_PCI_CTRL_PRO 0x0000000020000000ULL
#define TOM_PCI_CTRL_PRL 0x0000000010000000ULL
-#define SCZTOM_PCI_CTRL_PTO 0x0000000003000000ULL
-#define SCZTOM_PCI_CTRL_MMU_IEN 0x0000000000080000ULL
-#define SCZTOM_PCI_CTRL_SBH_IEN 0x0000000000040000ULL
-#define SCZTOM_PCI_CTRL_ERR_IEN 0x0000000000020000ULL
-#define SCZTOM_PCI_CTRL_ARB_PARK 0x0000000000010000ULL
+#define STX_PCI_CTRL_PTO 0x0000000003000000ULL
+#define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL
+#define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL
+#define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL
+#define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL
#define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL
-#define SCZTOM_PCI_CTRL_ARB_MASK 0x00000000000000ffULL
+#define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL
/* PCI asynchronous fault status register */
-#define SCZTOM_PCI_AFSR_P_MA 0x8000000000000000ULL
-#define SCZTOM_PCI_AFSR_P_TA 0x4000000000000000ULL
-#define SCZTOM_PCI_AFSR_P_RTRY 0x2000000000000000ULL
-#define SCZTOM_PCI_AFSR_P_PERR 0x1000000000000000ULL
-#define SCZTOM_PCI_AFSR_P_TTO 0x0800000000000000ULL
-#define SCZTOM_PCI_AFSR_P_UNUS 0x0400000000000000ULL
-#define SCZTOM_PCI_AFSR_S_MA 0x0200000000000000ULL
-#define SCZTOM_PCI_AFSR_S_TA 0x0100000000000000ULL
-#define SCZTOM_PCI_AFSR_S_RTRY 0x0080000000000000ULL
-#define SCZTOM_PCI_AFSR_S_PERR 0x0040000000000000ULL
-#define SCZTOM_PCI_AFSR_S_TTO 0x0020000000000000ULL
-#define SCZTOM_PCI_AFSR_S_UNUS 0x0010000000000000ULL
-#define SCZTOM_PCI_AFSR_DWMASK 0x0000030000000000ULL
-#define SCZTOM_PCI_AFSR_BMASK 0x000000ff00000000ULL
-#define SCZTOM_PCI_AFSR_BLK 0x0000000080000000ULL
-#define SCZTOM_PCI_AFSR_CFG 0x0000000040000000ULL
-#define SCZTOM_PCI_AFSR_MEM 0x0000000020000000ULL
-#define SCZTOM_PCI_AFSR_IO 0x0000000010000000ULL
+#define STX_PCI_AFSR_P_MA 0x8000000000000000ULL
+#define STX_PCI_AFSR_P_TA 0x4000000000000000ULL
+#define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL
+#define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL
+#define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL
+#define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL
+#define STX_PCI_AFSR_S_MA 0x0200000000000000ULL
+#define STX_PCI_AFSR_S_TA 0x0100000000000000ULL
+#define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL
+#define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL
+#define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL
+#define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL
+#define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL
+#define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL
+#define STX_PCI_AFSR_BLK 0x0000000080000000ULL
+#define STX_PCI_AFSR_CFG 0x0000000040000000ULL
+#define STX_PCI_AFSR_MEM 0x0000000020000000ULL
+#define STX_PCI_AFSR_IO 0x0000000010000000ULL
-#define SCZTOM_PCI_AFSR_ERRMASK \
- (SCZTOM_PCI_AFSR_P_MA | SCZTOM_PCI_AFSR_P_TA | \
- SCZTOM_PCI_AFSR_P_RTRY | SCZTOM_PCI_AFSR_P_PERR | \
- SCZTOM_PCI_AFSR_S_MA | SCZTOM_PCI_AFSR_S_TA | \
- SCZTOM_PCI_AFSR_S_RTRY | SCZTOM_PCI_AFSR_S_PERR)
+#define STX_PCI_AFSR_ERRMASK \
+ (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | STX_PCI_AFSR_P_RTRY | \
+ STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_S_MA | STX_PCI_AFSR_S_TA | \
+ STX_PCI_AFSR_S_RTRY | STX_PCI_AFSR_S_PERR)
/* PCI diagnostic register */
#define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL
-#define SCZTOM_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL
-#define SCZTOM_PCI_DIAG_TTO_DIS 0x0000000000000100ULL
+#define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL
+#define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL
#define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL
-#define SCZTOM_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL
-#define SCZTOM_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL
-#define SCZTOM_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL
-#define SCZTOM_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL
-#define SCZTOM_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL
+#define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL
+#define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL
+#define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL
+#define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL
+#define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL
/* Tomatillo I/O cache register */
#define TOM_PCI_IOC_PW 0x0000000000080000ULL
@@ -158,17 +157,17 @@
/* Controller configuration and status registers */
/* Note that these are shared on Schizo but per-PBM on Tomatillo. */
-#define SCZTOM_CTRL_BUS_ERRLOG 0x00018
-#define SCZTOM_CTRL_ECCCTRL 0x00020
-#define SCZTOM_CTRL_UE_AFSR 0x00030
-#define SCZTOM_CTRL_UE_AFAR 0x00038
-#define SCZTOM_CTRL_CE_AFSR 0x00040
-#define SCZTOM_CTRL_CE_AFAR 0x00048
-#define SCZTOM_CTRL_PERF 0x07000
-#define SCZTOM_CTRL_PERF_CNT 0x07008
+#define STX_CTRL_BUS_ERRLOG 0x00018
+#define STX_CTRL_ECCCTRL 0x00020
+#define STX_CTRL_UE_AFSR 0x00030
+#define STX_CTRL_UE_AFAR 0x00038
+#define STX_CTRL_CE_AFSR 0x00040
+#define STX_CTRL_CE_AFAR 0x00048
+#define STX_CTRL_PERF 0x07000
+#define STX_CTRL_PERF_CNT 0x07008
/* Safari/JBus error log register */
-#define SCZTOM_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL
+#define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL
#define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL
#define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL
#define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL
@@ -194,55 +193,55 @@
#define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL
#define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL
#define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL
-#define SCZTOM_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL
-#define SCZTOM_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL
-#define SCZTOM_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL
-#define SCZTOM_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL
+#define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL
+#define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL
+#define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL
+#define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL
#define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL
/* ECC control register */
-#define SCZTOM_CTRL_ECCCTRL_EE 0x8000000000000000ULL
-#define SCZTOM_CTRL_ECCCTRL_UE 0x4000000000000000ULL
-#define SCZTOM_CTRL_ECCCTRL_CE 0x2000000000000000ULL
+#define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL
+#define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL
+#define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL
/* Uncorrectable error asynchronous fault status register */
-#define SCZTOM_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL
-#define SCZTOM_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL
-#define SCZTOM_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL
-#define SCZTOM_CTRL_UE_AFSR_AID 0x000000001f000000ULL
-#define SCZTOM_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL
-#define SCZTOM_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL
-#define SCZTOM_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL
-#define SCZTOM_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL
-#define SCZTOM_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL
+#define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL
+#define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL
+#define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL
+#define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL
+#define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL
+#define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL
+#define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL
+#define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL
+#define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL
+#define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL
+#define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL
+#define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL
+#define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL
+#define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL
+#define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL
/* Correctable error asynchronous fault status register */
-#define SCZTOM_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL
-#define SCZTOM_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL
-#define SCZTOM_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL
-#define SCZTOM_CTRL_CE_AFSR_AID 0x000000001f000000ULL
-#define SCZTOM_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL
-#define SCZTOM_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL
-#define SCZTOM_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL
-#define SCZTOM_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL
-#define SCZTOM_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL
+#define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL
+#define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL
+#define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL
+#define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL
+#define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL
+#define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL
+#define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL
+#define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL
+#define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL
+#define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL
+#define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL
+#define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL
+#define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL
+#define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL
+#define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL
-#define SCZTOM_CTRL_CE_AFSR_ERRMASK \
- (SCZTOM_CTRL_CE_AFSR_P_PIO | SCZTOM_CTRL_CE_AFSR_P_DRD | \
- SCZTOM_CTRL_CE_AFSR_P_DWR | SCZTOM_CTRL_CE_AFSR_S_PIO | \
- SCZTOM_CTRL_CE_AFSR_S_DRD | SCZTOM_CTRL_CE_AFSR_S_DWR)
+#define STX_CTRL_CE_AFSR_ERRMASK \
+ (STX_CTRL_CE_AFSR_P_PIO | STX_CTRL_CE_AFSR_P_DRD | \
+ STX_CTRL_CE_AFSR_P_DWR | STX_CTRL_CE_AFSR_S_PIO | \
+ STX_CTRL_CE_AFSR_S_DRD | STX_CTRL_CE_AFSR_S_DWR)
/*
* Safari/JBus performance control register
@@ -255,58 +254,58 @@
#define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL
#define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL
#define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL
-#define SCZTOM_CTRL_PERF_PCI_B 0x000000000000000fULL
-#define SCZTOM_CTRL_PERF_PCI_A 0x000000000000000eULL
-#define SCZTOM_CTRL_PERF_UPA 0x000000000000000dULL
-#define SCZTOM_CTRL_PERF_PIOINTRNL 0x000000000000000cULL
+#define STX_CTRL_PERF_PCI_B 0x000000000000000fULL
+#define STX_CTRL_PERF_PCI_A 0x000000000000000eULL
+#define STX_CTRL_PERF_UPA 0x000000000000000dULL
+#define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL
#define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL
-#define SCZTOM_CTRL_PERF_INTRS 0x000000000000000aULL
-#define SCZTOM_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL
-#define SCZTOM_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL
-#define SCZTOM_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL
-#define SCZTOM_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL
-#define SCZTOM_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL
+#define STX_CTRL_PERF_INTRS 0x000000000000000aULL
+#define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL
+#define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL
+#define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL
+#define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL
+#define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL
#define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL
-#define SCZTOM_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL
-#define SCZTOM_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL
-#define SCZTOM_CTRL_PERF_BUSCYC 0x0000000000000001ULL
-#define SCZTOM_CTRL_PERF_DIS 0x0000000000000000ULL
-#define SCZTOM_CTRL_PERF_CNT1_SHIFT 11
-#define SCZTOM_CTRL_PERF_CNT0_SHIFT 4
+#define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL
+#define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL
+#define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL
+#define STX_CTRL_PERF_DIS 0x0000000000000000ULL
+#define STX_CTRL_PERF_CNT1_SHIFT 11
+#define STX_CTRL_PERF_CNT0_SHIFT 4
/* Safari/JBus performance counter register */
-#define SCZTOM_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL
-#define SCZTOM_CTRL_PERF_CNT_CNT1_SHIFT 32
-#define SCZTOM_CTRL_PERF_CNT_CNT0_SHIFT 0
>>> TRUNCATED FOR MAIL (1000 lines) <<<
More information about the p4-projects
mailing list