PERFORCE change 112617 for review

[Oleksandr Tymoshenko]

http://perforce.freebsd.org/chv.cgi?CH=112617

Change 112617 by gonzo at gonzo_hq on 2007/01/06 19:36:40

	o Implement SYS___syscall. Handle byte order for mips32eb.

Affected files ...

.. //depot/projects/mips2/src/sys/mips/mips/trap.c#14 edit

Differences ...

==== //depot/projects/mips2/src/sys/mips/mips/trap.c#14 (text+ko) ====

@@ -354,6 +354,7 @@
 	struct sysent *callp;
 	int locked = 0;
 	int args_shift = 0;
+	int quad_syscall = 0;
 
 	PCPU_LAZY_INC(cnt.v_syscall);
 	td->td_pticks = 0;
@@ -384,7 +385,12 @@
 
 	/* TODO: implement */
 	if(code == SYS___syscall)
-		panic("SYS___syscall: to implement");
+	{
+		code = frame->tf_regs[TF_A0 + _QUAD_LOWWORD];
+		args_shift = 2;
+		quad_syscall = 1;
+	}
+
 
 	if (p->p_sysent->sv_mask)
 		code &= p->p_sysent->sv_mask;
@@ -433,14 +439,24 @@
 		KASSERT(td->td_ar == NULL, 
 		    ("returning from syscall with td_ar set!"));
 	}
+
 	switch (error) {
 	case 0: 
+#ifdef __MIPSEB__
+		if(quad_syscall && (code != SYS_lseek)) {
+			/*
+			 * 64-bit return, 32-bit syscall. Fixup byte order
+			 */
+			frame->tf_regs[TF_V0] = 0;
+			frame->tf_regs[TF_V1] = td->td_retval[0];
+		} else {
+			frame->tf_regs[TF_V0] = td->td_retval[0];
+			frame->tf_regs[TF_V1] = td->td_retval[1];
+		}
+#else
 		frame->tf_regs[TF_V0] = td->td_retval[0];
-		/* 
-		 * XXXMIPS: should we consider this case for 32-bit or
-		 * only for 64bits?
-		 */ 
 		frame->tf_regs[TF_V1] = td->td_retval[1];
+#endif
 		frame->tf_regs[TF_A3] = 0;
 		break;