PERFORCE change 94182 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=94182

Change 94182 by imp at imp_Speedy on 2006/03/28 17:34:11

	Nits

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_usartreg.h#6 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_usartreg.h#6 (text+ko) ====

@@ -91,28 +91,28 @@
 #define USART_IMR		0x10 /* Interrupt mask register */
 #define USART_CSR		0x14 /* Channel status register */
 
-#define USART_CSR_RXRDY		(1U << 0) /* Receiver ready */
-#define USART_CSR_TXRDY		(1U << 1) /* Transmitter ready */
-#define USART_CSR_RXBRK		(1U << 2) /* Break received */
-#define USART_CSR_ENDRX		(1U << 3) /* End of Transfer RX from PDC */
-#define USART_CSR_ENDTX		(1U << 4) /* End of Transfer TX from PDC */
-#define USART_CSR_OVRE		(1U << 5) /* Overrun error */
-#define USART_CSR_FRAME		(1U << 6) /* Framing error */
-#define USART_CSR_PARE		(1U << 7) /* Parity Error */
-#define USART_CSR_TIMEOUT	(1U << 8) /* Timeout since start-timeout */
-#define USART_CSR_TXEMPTY	(1U << 9) /* Transmitter empty */
-#define USART_CSR_ITERATION	(1U << 10) /* max repetitions since RSIT */
-#define USART_CSR_TXBUFE	(1U << 11) /* Buffer empty from PDC */
-#define USART_CSR_RXBUFF	(1U << 12) /* Buffer full from PDC */
-#define USART_CSR_NACK		(1U << 13) /* NACK since last RSTNACK */
-#define USART_CSR_RIIC		(1U << 16) /* RI delta since last csr read */
-#define USART_CSR_DSRIC		(1U << 17) /* DSR delta */
-#define USART_CSR_DCDIC		(1U << 18) /* DCD delta */
-#define USART_CSR_CTSIC		(1U << 19) /* CTS delta */
-#define USART_CSR_RI		(1U << 20) /* RI status */
-#define USART_CSR_DSR		(1U << 21) /* DSR status */
-#define USART_CSR_DCD		(1U << 22) /* DCD status */
-#define USART_CSR_CTS		(1U << 23) /* CTS status */
+#define USART_CSR_RXRDY		(1UL << 0) /* Receiver ready */
+#define USART_CSR_TXRDY		(1UL << 1) /* Transmitter ready */
+#define USART_CSR_RXBRK		(1UL << 2) /* Break received */
+#define USART_CSR_ENDRX		(1UL << 3) /* End of Transfer RX from PDC */
+#define USART_CSR_ENDTX		(1UL << 4) /* End of Transfer TX from PDC */
+#define USART_CSR_OVRE		(1UL << 5) /* Overrun error */
+#define USART_CSR_FRAME		(1UL << 6) /* Framing error */
+#define USART_CSR_PARE		(1UL << 7) /* Parity Error */
+#define USART_CSR_TIMEOUT	(1UL << 8) /* Timeout since start-timeout */
+#define USART_CSR_TXEMPTY	(1UL << 9) /* Transmitter empty */
+#define USART_CSR_ITERATION	(1UL << 10) /* max repetitions since RSIT */
+#define USART_CSR_TXBUFE	(1UL << 11) /* Buffer empty from PDC */
+#define USART_CSR_RXBUFF	(1UL << 12) /* Buffer full from PDC */
+#define USART_CSR_NACK		(1UL << 13) /* NACK since last RSTNACK */
+#define USART_CSR_RIIC		(1UL << 16) /* RI delta since last csr read */
+#define USART_CSR_DSRIC		(1UL << 17) /* DSR delta */
+#define USART_CSR_DCDIC		(1UL << 18) /* DCD delta */
+#define USART_CSR_CTSIC		(1UL << 19) /* CTS delta */
+#define USART_CSR_RI		(1UL << 20) /* RI status */
+#define USART_CSR_DSR		(1UL << 21) /* DSR status */
+#define USART_CSR_DCD		(1UL << 22) /* DCD status */
+#define USART_CSR_CTS		(1UL << 23) /* CTS status */
 
 #define USART_RHR		0x18 /* Receiver holding register */
 #define USART_THR		0x1c /* Transmitter holding register */