PERFORCE change 94148 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=94148

Change 94148 by imp at imp_hammer on 2006/03/28 08:43:33

	checkpoint

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_usartreg.h#5 edit
.. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#16 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_usartreg.h#5 (text+ko) ====

@@ -28,24 +28,24 @@
 #define AT91USARTREG_H_
 
 #define USART_CR		0x00 /* Control register */
-#define USART_CR_RSTRX		(1 << 2) /* Reset Receiver */
-#define USART_CR_RSTTX		(1 << 3) /* Reset Transmitter */
-#define USART_CR_RXEN		(1 << 4) /* Receiver Enable */
-#define USART_CR_RXDIS		(1 << 5) /* Receiver Disable */
-#define USART_CR_TXEN		(1 << 6) /* Transmitter Enable */
-#define USART_CR_TXDIS		(1 << 7) /* Transmitter Disable */
-#define USART_CR_RSTSTA		(1 << 8) /* Reset Status Bits */
-#define USART_CR_STTBRK		(1 << 9) /* Start Break */
-#define USART_CR_STPBRK		(1 << 10) /* Stop Break */
-#define USART_CR_STTTO		(1 << 11) /* Start Time-out */
-#define USART_CR_SENDA		(1 << 12) /* Send Address */
-#define USART_CR_RSTIT		(1 << 13) /* Reset Iterations */
-#define USART_CR_RSTNACK	(1 << 14) /* Reset Non Acknowledge */
-#define USART_CR_RETTO		(1 << 15) /* Rearm Time-out */
-#define USART_CR_DTREN		(1 << 16) /* Data Terminal ready Enable */
-#define USART_CR_DTRDIS		(1 << 17) /* Data Terminal ready Disable */
-#define USART_CR_RTSEN		(1 << 18) /* Request to Send enable */
-#define USART_CR_RTSDIS		(1 << 19) /* Request to Send Disable */
+#define USART_CR_RSTRX		(1UL << 2) /* Reset Receiver */
+#define USART_CR_RSTTX		(1UL << 3) /* Reset Transmitter */
+#define USART_CR_RXEN		(1UL << 4) /* Receiver Enable */
+#define USART_CR_RXDIS		(1UL << 5) /* Receiver Disable */
+#define USART_CR_TXEN		(1UL << 6) /* Transmitter Enable */
+#define USART_CR_TXDIS		(1UL << 7) /* Transmitter Disable */
+#define USART_CR_RSTSTA		(1UL << 8) /* Reset Status Bits */
+#define USART_CR_STTBRK		(1UL << 9) /* Start Break */
+#define USART_CR_STPBRK		(1UL << 10) /* Stop Break */
+#define USART_CR_STTTO		(1UL << 11) /* Start Time-out */
+#define USART_CR_SENDA		(1UL << 12) /* Send Address */
+#define USART_CR_RSTIT		(1UL << 13) /* Reset Iterations */
+#define USART_CR_RSTNACK	(1UL << 14) /* Reset Non Acknowledge */
+#define USART_CR_RETTO		(1UL << 15) /* Rearm Time-out */
+#define USART_CR_DTREN		(1UL << 16) /* Data Terminal ready Enable */
+#define USART_CR_DTRDIS		(1UL << 17) /* Data Terminal ready Disable */
+#define USART_CR_RTSEN		(1UL << 18) /* Request to Send enable */
+#define USART_CR_RTSDIS		(1UL << 19) /* Request to Send Disable */
 
 #define USART_MR		0x04 /* Mode register */
 #define USART_MR_MODE_NORMAL	0	/* Normal/Async/3-wire rs-232 */
@@ -125,24 +125,4 @@
 /* 0x48 reserved */
 #define USART_IFR		0x48 /* IrDA filter register */
 
-
-#define UART_RXRDY		(0x1 << 0)	/* RXRDY Interrupt */
-#define UART_TXRDY		(0x1 << 1)	/* TXRDY Interrupt */
-#define UART_RXBRK		(0x1 << 2)	/* Break Received/End of Break */
-#define UART_ENDRX		(0x1 << 3)	/* End of Receive Transfer Interrupt */
-#define UART_ENDTX		(0x1 << 4)	/* End of Transmit Interrupt */
-#define UART_OVRE		(0x1 << 5)	/* Overrun Interrupt */
-#define UART_FRAME		(0x1 << 6)	/* Framing Error Interrupt */
-#define UART_PARE		(0x1 << 7)	/* Parity Error Interrupt */
-#define UART_TIMEOUT	( 0x1 << 8)	/* (USART) Receiver Time-out */
-#define UART_TXEMPTY      ( 0x1 << 9)	/* (USART) TXEMPTY Interrupt */
-#define UART_ITERATION    ( 0x1 << 10)	/* (USART) Max number of Repetitions Reached */
-#define UART_TXBUFE       ( 0x1 << 11)	/* (USART) TXBUFE Interrupt */
-#define UART_RXBUFF       ( 0x1 << 12)	/* (USART) RXBUFF Interrupt */
-#define UART_NACK         ( 0x1 << 13)	/* (USART) Non Acknowledge */
-#define UART_RIIC         ( 0x1 << 16)	/* (USART) Ring INdicator Input Change Flag */
-#define AT91RM92_US_DSRIC        ( 0x1 << 17)	/* (USART) Data Set Ready Input Change Flag */
-#define AT91RM92_US_DCDIC        ( 0x1 << 18)	/* (USART) Data Carrier Flag */
-#define AT91RM92_US_CTSIC        ( 0x1 << 19)	/* (USART) Clear To Send Input Change Flag */
-
 #endif /* AT91RM92REG_H_ */

==== //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#16 (text+ko) ====

@@ -274,8 +274,8 @@
 static int
 at91_usart_bus_attach(struct uart_softc *sc)
 {
-	sc->sc_txfifosz = 32;
-	sc->sc_rxfifosz = 1;
+	sc->sc_txfifosz = 128;	/* Really 64k, but 128 seems a good number */
+	sc->sc_rxfifosz = 128;
 	sc->sc_hwiflow = 0;
 	return (0);
 }
@@ -287,8 +287,15 @@
 	/* XXX VERY sub-optimial */
 	mtx_lock_spin(&sc->sc_hwmtx);
 	sc->sc_txbusy = 1;
+#if 0
+	/* XXX
+	 * We can setup the PDC to transfer the whole buffer
+	 * here.
+	 */
+#else
 	for (i = 0; i < sc->sc_txdatasz; i++)
 		at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
+#endif
 	mtx_unlock_spin(&sc->sc_hwmtx);
 #ifdef USART0_CONSOLE
 	/*