PERFORCE change 92669 for review
Kip Macy
kmacy at FreeBSD.org
Thu Mar 2 21:28:33 PST 2006
http://perforce.freebsd.org/chv.cgi?CH=92669
Change 92669 by kmacy at kmacy_storage:sun4v_work on 2006/03/03 05:27:39
C code should not be executed at tl > 0, fix kernel trap / interrupt handling
so that handlers are executed at tl0
Affected files ...
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asm.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asmacros.h#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/hypervisor_api.h#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/pcpu.h#5 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tstate.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#13 edit
Differences ...
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asm.h#2 (text+ko) ====
@@ -101,6 +101,7 @@
#define WINDOWSIZE64 (16*8)
#define MINFRAME64 (WINDOWSIZE64 + 48)
#define MINFRAME MINFRAME64
+#define REGOFF SA(MINFRAME)
/*
* Kernel RCS ID tag and copyright macros
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asmacros.h#3 (text+ko) ====
@@ -1,5 +1,6 @@
/*-
* Copyright (c) 2001 Jake Burkholder.
+ * Copyright (c) 2006 Kip Macy
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -146,9 +147,43 @@
GET_PCPU_SCRATCH; \
ldx [PCPU_REG + PC_CURPCB], reg;
-#define SAVE_V8_WINDOW(reg)
+#define SAVE_GLOBALS(TF) \
+ stx %g1, [TF + TF_G1]; \
+ stx %g2, [TF + TF_G2]; \
+ stx %g3, [TF + TF_G3]; \
+ stx %g4, [TF + TF_G4]; \
+ stx %g5, [TF + TF_G5]; \
+ stx %g6, [TF + TF_G6]; \
+ stx %g7, [TF + TF_G7];
+#define RESTORE_GLOBALS(TF) \
+ ldx [TF + TF_G1], %g1; \
+ ldx [TF + TF_G2], %g2; \
+ ldx [TF + TF_G3], %g3; \
+ ldx [TF + TF_G4], %g4; \
+ ldx [TF + TF_G5], %g5; \
+ ldx [TF + TF_G6], %g6; \
+ ldx [TF + TF_G7], %g7;
+#define SAVE_OUTS(TF) \
+ stx %i0, [TF + TF_O0]; \
+ stx %i1, [TF + TF_O1]; \
+ stx %i2, [TF + TF_O2]; \
+ stx %i3, [TF + TF_O3]; \
+ stx %i4, [TF + TF_O4]; \
+ stx %i5, [TF + TF_O5]; \
+ stx %i6, [TF + TF_O6]; \
+ stx %i7, [TF + TF_O7];
+
+#define RESTORE_OUTS(TF) \
+ ldx [TF + TF_O0], %i0; \
+ ldx [TF + TF_O1], %i1; \
+ ldx [TF + TF_O2], %i2; \
+ ldx [TF + TF_O3], %i3; \
+ ldx [TF + TF_O4], %i4; \
+ ldx [TF + TF_O5], %i5; \
+ ldx [TF + TF_O6], %i6; \
+ ldx [TF + TF_O7], %i7;
#endif /* LOCORE */
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/hypervisor_api.h#3 (text+ko) ====
@@ -91,6 +91,9 @@
extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state);
extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid);
extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid);
+extern void hv_magic_trap_on(void);
+extern void hv_magic_trap_off(void);
+
#endif
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/pcpu.h#5 (text+ko) ====
@@ -71,6 +71,9 @@
u_long pc_tickref; \
u_long pc_tickadj; \
u_int pc_mid; \
+ struct rwindow pc_kwbuf; \
+ u_long pc_kwbuf_sp; \
+ u_int pc_kwbuf_full; \
u_int pc_node; \
u_int pc_tlb_ctx; \
u_int pc_tlb_ctx_max; \
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tstate.h#2 (text+ko) ====
@@ -54,6 +54,8 @@
#define TSTATE_CLE TSTATE_PSTATE(PSTATE_CLE)
#define TSTATE_MG TSTATE_PSTATE(PSTATE_MG)
#define TSTATE_IG TSTATE_PSTATE(PSTATE_IG)
+#define TSTATE_KERNEL TSTATE_PSTATE(PSTATE_KERNEL)
+
#define TSTATE_ASI_SHIFT 24
#define TSTATE_ASI_BITS 8
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#13 (text+ko) ====
@@ -81,7 +81,8 @@
#define MAGIC_TRAP_ON nop
#define MAGIC_TRAP_OFF nop
#endif
-
+
+#define REGSIZE 8
#define TSB_KERNEL_MASK 0x0
#define TSB_KERNEL 0x0
@@ -124,7 +125,6 @@
*/
#define SPILL(storer, bias, size, asi) \
- SPILL_FILL_MAGIC_TRAP_ON ;\
mov 0 + bias, %g1 ;\
storer %l0, [%sp + %g1]asi ;\
mov size + bias, %g2 ;\
@@ -150,7 +150,6 @@
storer %i7, [%g5 + %g4]asi
#define FILL(loader, bias, size, asi) \
- SPILL_FILL_MAGIC_TRAP_ON ;\
mov 0 + bias, %g1 ;\
loader [%sp + %g1]asi, %l0 ;\
mov size + bias, %g2 ;\
@@ -428,32 +427,14 @@
.align 128
.endm
- /*
- * Stack fixups for entry from user mode. We are still running on the
- * user stack, and with its live registers, so we must save soon. We
- * are on alternate globals so we do have some registers. Set the
- * transitional window state, and do the save. If this traps we
- * we attempt to spill a window to the user stack. If this fails,
- * we spill the window to the pcb and continue. Spilling to the pcb
- * must not fail.
- *
- * NOTE: Must be called with alternate globals and clobbers %g1.
- */
-
.macro tl0_split
-#if 0
- rdpr %wstate, %g1
- wrpr %g1, WSTATE_TRANSITION, %wstate
- save
-#endif
+ GET_PCB(PCB_REG); /* load PCPU and PCB pointers */
.endm
.macro tl0_setup type
tl0_split
- clr %o1
- set trap, %o2
ba %xcc, tl0_utrap
- mov \type, %o0
+ mov \type, %g1
.endm
/*
@@ -564,15 +545,17 @@
#define spill_32bit_asi(asi, target) \
srl %sp, 0, %sp ; \
+ SPILL_FILL_MAGIC_TRAP_ON; \
SPILL(sta, 0, 4, asi) ; \
saved ; \
- MAGIC_TRAP_OFF ; \
+ SPILL_FILL_MAGIC_TRAP_OFF; \
retry ; \
.skip (31-28)*4 ; \
ba,a,pt %xcc, fault_32bit_##target ; \
ALIGN_128
#define spill_64bit_asi(asi, target) \
+ SPILL_FILL_MAGIC_TRAP_ON ; \
SPILL(stxa, SPOFF, 8, asi) ; \
saved ; \
SPILL_FILL_MAGIC_TRAP_OFF ; \
@@ -583,6 +566,7 @@
#define spill_32clean(asi, target) \
srl %sp, 0, %sp ; \
+ SPILL_FILL_MAGIC_TRAP_ON; \
SPILL(sta, 0, 4, asi) ; \
b spill_clean ; \
mov WSTATE_USER32, %g7 ; \
@@ -591,6 +575,7 @@
ALIGN_128
#define spill_64clean(asi, target) \
+ SPILL_FILL_MAGIC_TRAP_ON; \
SPILL(stxa, SPOFF, 8, asi) ; \
b spill_clean ; \
mov WSTATE_USER64, %g7 ; \
@@ -600,6 +585,7 @@
#define fill_32bit_asi(asi, target) \
srl %sp, 0, %sp ; \
+ SPILL_FILL_MAGIC_TRAP_ON; \
FILL(lda, 0, 4, asi) ; \
restored ; \
retry ; \
@@ -608,6 +594,7 @@
ALIGN_128
#define fill_64bit_asi(asi, target) \
+ SPILL_FILL_MAGIC_TRAP_ON; \
FILL(ldxa, SPOFF, 8, asi) ; \
restored ; \
SPILL_FILL_MAGIC_TRAP_OFF ; \
@@ -730,19 +717,27 @@
mov %g2, %o0
END(tl0_sfsr_trap)
- .macro tl0_intr level, mask
+ .macro tl0_pil_entry level, mask
+ tl0_split
+ set \mask, %g2
+ ba %xcc, tl0_intr
+ mov \level, %g1
+ .align 32
+ .endm
+
+ .macro tl1_pil_entry level, mask
tl0_split
- set \mask, %o1
+ set \mask, %g2
ba %xcc, tl0_intr
- mov \level, %o0
+ mov \level, %g1
.align 32
.endm
#define INTR(level, traplvl) \
- tl ## traplvl ## _intr level, 1 << level
+ tl ## traplvl ## _pil_entry level, 1 << level
#define TICK(traplvl) \
- tl ## traplvl ## _intr PIL_TICK, 1
+ tl ## traplvl ## _pil_entry PIL_TICK, 1
#define INTR_LEVEL(tl) \
INTR(1, tl) ; \
@@ -758,10 +753,11 @@
INTR(11, tl) ; \
INTR(12, tl) ; \
INTR(13, tl) ; \
+tick_ ## tl ## _entry: \
TICK(tl) ; \
INTR(15, tl) ;
- .macro tl0_intr_level
+ .macro tl0_pil
INTR_LEVEL(0)
.endm
@@ -1748,7 +1744,7 @@
tl0_gen T_PRIVILEGED_ACTION ! 0x37
tl0_reserved 9 ! 0x38-0x40
tl0_intr_level_41:
- tl0_intr_level ! 0x41-0x4f
+ tl0_pil ! 0x41-0x4f
tl0_reserved 18 ! 0x50-0x61
tl0_watch_virt_62:
tl0_gen T_VA_WATCHPOINT ! 0x62
@@ -1943,6 +1939,7 @@
* If the trap type allows user traps, setup state to execute the user trap
* handler and bounce back to usermode, otherwise branch to tl0_trap.
*/
+#if 0
ENTRY(tl0_utrap)
/*
* Check if the trap type allows user traps.
@@ -2034,7 +2031,7 @@
*/
done
END(tl0_utrap)
-
+#endif
/*
* (Real) User trap entry point.
*
@@ -2054,209 +2051,212 @@
* the normal %g7 *before* enabling interrupts. This avoids any possibility
* of cpu migration and using the wrong pcpup.
*/
-ENTRY(tl0_trap)
- GET_PCB(PCB_REG)
-
- rdpr %tstate, %l0
- rdpr %tpc, %l1
- rdpr %tnpc, %l2
- rd %y, %l3
- rd %fprs, %l4
- rdpr %wstate, %l5
-#if KTR_COMPILE & KTR_TRAP
- CATR(KTR_TRAP,
- "tl0_trap: td=%p type=%#x pil=%#lx pc=%#lx npc=%#lx sp=%#lx"
- , %g1, %g2, %g3, 7, 8, 9)
- ldx [PCPU(CURTHREAD)], %g2
- stx %g2, [%g1 + KTR_PARM1]
- stx %o0, [%g1 + KTR_PARM2]
- rdpr %pil, %g2
- stx %g2, [%g1 + KTR_PARM3]
- stx %l1, [%g1 + KTR_PARM4]
- stx %l2, [%g1 + KTR_PARM5]
- stx %i6, [%g1 + KTR_PARM6]
-9:
-#endif
-#if 0
-1: and %l5, WSTATE_NORMAL_MASK, %l5
- sllx %l5, WSTATE_OTHER_SHIFT, %l5
- wrpr %l5, WSTATE_KERNEL, %wstate
-#endif
- rdpr %canrestore, %l6
- wrpr %l6, 0, %otherwin
- wrpr %g0, 0, %canrestore
- sub PCB_REG, SPOFF + CCFSZ + TF_SIZEOF, %sp
+
+#define KWBUF64_TO_STACK(SBP,SPP,TMP) \
+ ldx [SBP + (0*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 0]; \
+ ldx [SBP + (1*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 8]; \
+ ldx [SBP + (2*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 16]; \
+ ldx [SBP + (3*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 24]; \
+ ldx [SBP + (4*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 32]; \
+ ldx [SBP + (5*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 40]; \
+ ldx [SBP + (6*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 48]; \
+ ldx [SBP + (7*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 56]; \
+ ldx [SBP + (8*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 64]; \
+ ldx [SBP + (9*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 72]; \
+ ldx [SBP + (10*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 80]; \
+ ldx [SBP + (11*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 88]; \
+ ldx [SBP + (12*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 96]; \
+ ldx [SBP + (13*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 104]; \
+ ldx [SBP + (14*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 112]; \
+ ldx [SBP + (15*8)], TMP; \
+ stx TMP, [SPP + SPOFF + 120];
- stx %o0, [%sp + SPOFF + CCFSZ + TF_TYPE]
- stx %o1, [%sp + SPOFF + CCFSZ + TF_LEVEL]
- stx %o3, [%sp + SPOFF + CCFSZ + TF_TAR]
- stx %o4, [%sp + SPOFF + CCFSZ + TF_SFAR]
- stx %o5, [%sp + SPOFF + CCFSZ + TF_SFSR]
- stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
- stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
- stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
- stx %l3, [%sp + SPOFF + CCFSZ + TF_Y]
- stx %l4, [%sp + SPOFF + CCFSZ + TF_FPRS]
- stx %l5, [%sp + SPOFF + CCFSZ + TF_WSTATE]
+#define fill_64bit_rtt(asi_num) \
+ wr %g0, asi_num, %asi ;\
+ rdpr %cwp, %g1 ;\
+ sub %g1, 1, %g1 ;\
+ wrpr %g1, %cwp ;\
+ ldxa [%sp + SPOFF + 0]%asi, %l0 ;\
+ ldxa [%sp + SPOFF + 8]%asi, %l1 ;\
+ ldxa [%sp + SPOFF + 16]%asi, %l2 ;\
+ ldxa [%sp + SPOFF + 24]%asi, %l3 ;\
+ ldxa [%sp + SPOFF + 32]%asi, %l4 ;\
+ ldxa [%sp + SPOFF + 40]%asi, %l5 ;\
+ ldxa [%sp + SPOFF + 48]%asi, %l6 ;\
+ ldxa [%sp + SPOFF + 56]%asi, %l7 ;\
+ ldxa [%sp + SPOFF + 64]%asi, %i0 ;\
+ ldxa [%sp + SPOFF + 72]%asi, %i1 ;\
+ ldxa [%sp + SPOFF + 80]%asi, %i2 ;\
+ ldxa [%sp + SPOFF + 88]%asi, %i3 ;\
+ ldxa [%sp + SPOFF + 96]%asi, %i4 ;\
+ ldxa [%sp + SPOFF + 104]%asi, %i5 ;\
+ ldxa [%sp + SPOFF + 112]%asi, %i6 ;\
+ ldxa [%sp + SPOFF + 120]%asi, %i7 ;\
+ restored ;\
+ add %g1, 1, %g1 ;\
+ wrpr %g1, %cwp
- wr %g0, FPRS_FEF, %fprs
- stx %fsr, [%sp + SPOFF + CCFSZ + TF_FSR]
- rd %gsr, %l6
- stx %l6, [%sp + SPOFF + CCFSZ + TF_GSR]
- wr %g0, 0, %fprs
+
- mov PCB_REG, %l0
- mov PCPU_REG, %l1
- wrpr %g0, PSTATE_NORMAL, %pstate
+ENTRY(ktl0)
+ SAVE_GLOBALS(%l7)
+ SAVE_OUTS(%l7) ! for the call bug workaround
+ wrpr %g0, PSTATE_KERNEL, %pstate ! enable ints
+! MAGIC_TRAP_OFF
+ call critical_enter
+ nop
+ jmpl %l3, %o7 ! call trap handler
+ mov %l7, %o0
+ call critical_exit
+ nop
+! MAGIC_TRAP_ON
+ENTRY(krtt)
+ GET_PCPU_SCRATCH
+common_rtt:
+ !
+ ! restore globals and outs
+ !
+ rdpr %pstate, %l1
+ wrpr %l1, PSTATE_IE, %pstate
+ RESTORE_GLOBALS(%l7)
+ ! switch to global set 1
+ wrpr %g0, 1, %gl
+ RESTORE_OUTS(%l7)
+#ifdef notyet
+ !
+ ! set %pil from max(old pil, cur_thread_spl)
+ !
+ ldn [%l0 + T_CPU], %l0
+ ld [%l0 + CPU_BASE_SPL], %l0
+ cmp %l6, %l0
+ movg %xcc, %l6, %l0
+ wrpr %g0, %l0, %pil
+#endif
+ !
+ ! raise tl
+ ! setup trap regs
+ ! restore to window we originally trapped in
+ !
+ wrpr %g0, 1, %tl
+ ldx [%l7 + TF_TPC], %g1
+ ldx [%l7 + TF_TNPC], %g2
+ ldx [%l7 + TF_TSTATE], %l0
+ andn %l0, TSTATE_CWP_MASK, %g4
+ wrpr %g1, %tpc
+ wrpr %g2, %tnpc
+ rdpr %canrestore, %g1
+ brnz %g1, 3f
+ nop ! can use restore directly
+ rdpr %cwp, %g1
+ wrpr %g1, %g4, %tstate ! needed by wbuf recovery code
- stx PCB_REG, [%sp + SPOFF + CCFSZ + TF_G6]
- stx %g7, [%sp + SPOFF + CCFSZ + TF_G7]
+ ! avoid going above TL2
+ fill_64bit_rtt(ASI_N)
- mov %l0, PCB_REG
- mov %l1, PCPU_REG
- wrpr %g0, PSTATE_KERNEL, %pstate
+3:
+ restore
+ !
+ ! set %tstate to the correct %cwp
+ !
+ rdpr %cwp, %g1
+ wrpr %g1, %g4, %tstate
+ retry
+END(krtt)
+END(ktl0)
+
+ ! temporaries: %g3-%g5
+ !
+ !
+ENTRY(tl0_ktrap)
+ set ktl0, %g4
+ save %sp, -(CCFSZ + TF_SIZEOF), %sp
- stx %i0, [%sp + SPOFF + CCFSZ + TF_O0]
- stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
- stx %i2, [%sp + SPOFF + CCFSZ + TF_O2]
- stx %i3, [%sp + SPOFF + CCFSZ + TF_O3]
- stx %i4, [%sp + SPOFF + CCFSZ + TF_O4]
- stx %i5, [%sp + SPOFF + CCFSZ + TF_O5]
- stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
- stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
+ mov %g2, %l3 ! set trap/interrupt for tl0
+
+ ! if the kwbuf is full we need to save to the stack now
+ ld [PCPU_REG + PC_KWBUF_FULL], %o0
+ brz,pt %o0, 1f
+ nop
+ st %g0, [PCPU_REG + PC_KWBUF_FULL]
+ ldx [PCPU_REG + PC_KWBUF_SP], %o1
+ add PCPU_REG, PC_KWBUF, %o0
+ KWBUF64_TO_STACK(%o0, %o1, %o2)
+1:
+ ba,a,pt %xcc, win_saved
+END(tl0_ktrap)
+
- stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
- stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
- stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
- stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
- stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
-
- set tl0_ret - 8, %o7
- jmpl %o2, %g0
- add %sp, CCFSZ + SPOFF, %o0
-END(tl0_trap)
-
-/*
- * void tl0_intr(u_int level, u_int mask)
- */
+ ! register convention:
+ ! %g1=level %g2=mask
+
ENTRY(tl0_intr)
- GET_PCB(PCB_REG)
+ wrpr %g1, 0, %pil
+ wr %g2, 0, %clear_softint
+ SET(intr_handlers, %g5, %g4)
+ sllx %g1, IH_SHIFT, %g5
+ ldx [%g4 + %g5], %g2 ! pointer to interrupt handler
- rdpr %tstate, %l0
- rdpr %tpc, %l1
- rdpr %tnpc, %l2
- rd %y, %l3
- rd %fprs, %l4
- rdpr %wstate, %l5
+
+
+ ! assumes %g3 - %g5 are free
+ ! %g1 == pil that we came in on
+ ! %g2 == interrupt handler
+ ! %g6 == PCB
+ ! %g7 == PCPU
+ ! %g3-%g5 temporaries
+ENTRY(tl0_trap)
+ rdpr %tstate, %g3
+ btst TSTATE_PRIV, %g3
+ and %g3, TSTATE_CWP_MASK, %g4
+ bnz,pn %xcc, tl0_ktrap
+ wrpr %g0, %g4, %cwp
+ENTRY(tl0_utrap)
+ illtrap
-#if KTR_COMPILE & KTR_INTR
- CATR(KTR_INTR,
- "tl0_intr: td=%p level=%#x pil=%#lx pc=%#lx npc=%#lx sp=%#lx"
- , %g1, %g2, %g3, 7, 8, 9)
- ldx [PCPU(CURTHREAD)], %g2
- stx %g2, [%g1 + KTR_PARM1]
- stx %o0, [%g1 + KTR_PARM2]
- rdpr %pil, %g2
- stx %g2, [%g1 + KTR_PARM3]
- stx %l1, [%g1 + KTR_PARM4]
- stx %l2, [%g1 + KTR_PARM5]
- stx %i6, [%g1 + KTR_PARM6]
-9:
-#endif
-
- wrpr %o0, 0, %pil
- wr %o1, 0, %clear_softint
-
-#if 0
- and %l5, WSTATE_NORMAL_MASK, %l5
- sllx %l5, WSTATE_OTHER_SHIFT, %l5
- wrpr %l5, WSTATE_KERNEL, %wstate
-#endif
- rdpr %canrestore, %l6
- wrpr %l6, 0, %otherwin
- wrpr %g0, 0, %canrestore
-
- sub PCB_REG, SPOFF + CCFSZ + TF_SIZEOF, %sp
-
- stx %l0, [%sp + SPOFF + CCFSZ + TF_TSTATE]
- stx %l1, [%sp + SPOFF + CCFSZ + TF_TPC]
- stx %l2, [%sp + SPOFF + CCFSZ + TF_TNPC]
- stx %l3, [%sp + SPOFF + CCFSZ + TF_Y]
- stx %l4, [%sp + SPOFF + CCFSZ + TF_FPRS]
- stx %l5, [%sp + SPOFF + CCFSZ + TF_WSTATE]
-
- wr %g0, FPRS_FEF, %fprs
- stx %fsr, [%sp + SPOFF + CCFSZ + TF_FSR]
- rd %gsr, %l6
- stx %l6, [%sp + SPOFF + CCFSZ + TF_GSR]
- wr %g0, 0, %fprs
-
- mov %o0, %l3
- mov T_INTERRUPT, %o1
-
- stx %o0, [%sp + SPOFF + CCFSZ + TF_LEVEL]
- stx %o1, [%sp + SPOFF + CCFSZ + TF_TYPE]
-
- mov PCB_REG, %l0
- mov PCPU_REG, %l1
- wrpr %g0, PSTATE_NORMAL, %pstate
-
- stx %g1, [%sp + SPOFF + CCFSZ + TF_G1]
- stx %g2, [%sp + SPOFF + CCFSZ + TF_G2]
- stx %g3, [%sp + SPOFF + CCFSZ + TF_G3]
- stx %g4, [%sp + SPOFF + CCFSZ + TF_G4]
- stx %g5, [%sp + SPOFF + CCFSZ + TF_G5]
- stx %g6, [%sp + SPOFF + CCFSZ + TF_G6]
- stx %g7, [%sp + SPOFF + CCFSZ + TF_G7]
-
- mov %l0, PCB_REG
- mov %l1, PCPU_REG
- wrpr %g0, PSTATE_KERNEL, %pstate
-
- stx %i0, [%sp + SPOFF + CCFSZ + TF_O0]
- stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
- stx %i2, [%sp + SPOFF + CCFSZ + TF_O2]
- stx %i3, [%sp + SPOFF + CCFSZ + TF_O3]
- stx %i4, [%sp + SPOFF + CCFSZ + TF_O4]
- stx %i5, [%sp + SPOFF + CCFSZ + TF_O5]
- stx %i6, [%sp + SPOFF + CCFSZ + TF_O6]
- stx %i7, [%sp + SPOFF + CCFSZ + TF_O7]
-
- /* %l3 contains PIL */
- SET(intrcnt, %l1, %l2)
- prefetcha [%l2] ASI_N, 1
- SET(pil_countp, %l1, %l0)
- sllx %l3, 1, %l1
- lduh [%l0 + %l1], %l0
- sllx %l0, 3, %l0
- add %l0, %l2, %l0
- ldx [%l0], %l1
- inc %l1
- stx %l1, [%l0]
-
- call critical_enter
- nop
-
- lduw [PCPU(CNT) + V_INTR], %l0
- inc %l0
- stw %l0, [PCPU(CNT) + V_INTR]
-
- SET(intr_handlers, %l1, %l0)
- sllx %l3, IH_SHIFT, %l1
- ldx [%l0 + %l1], %l1
- KASSERT(%l1, "tl0_intr: ih null")
- call %l1
- add %sp, CCFSZ + SPOFF, %o0
-
- call critical_exit
- nop
-
- ba,a %xcc, tl0_ret
- nop
+win_saved:
+ !
+ ! save trap state on stack
+ !
+ add %sp, REGOFF + SPOFF, %l7
+ rdpr %tpc, %l0
+ rdpr %tnpc, %l1
+ rdpr %tstate, %l2
+ stx %l0, [%l7 + TF_TPC]
+ stx %l1, [%l7 + TF_TNPC]
+ stx %l2, [%l7 + TF_TSTATE]
+ !
+ ! setup pil
+ !
+ brlz,pt %g1, 1f
+ nop
+ wrpr %g0, %g1, %pil
+
+ wrpr %g0, %g4, %tnpc
+ rdpr %cwp, %l0
+ set TSTATE_KERNEL, %l1
+ wrpr %l1, %l0, %tstate
+ done
+END(tl0_utrap)
+END(tl0_trap)
END(tl0_intr)
/*
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