PERFORCE change 89887 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=89887

Change 89887 by imp at imp_hammer on 2006/01/18 05:34:25

	Add-in the bits for this device, wakeup sc in the interrupt handler,
	include register definitions.
	
	# Still need to write a userland interface for this device.

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_twi.c#2 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#2 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_twi.c#2 (text+ko) ====

@@ -37,6 +37,8 @@
 #include <sys/rman.h>
 #include <machine/bus.h>
 
+#include <arm/at91/at91_twireg.h>
+
 struct at91_twi_softc
 {
 	device_t dev;			/* Myself */
@@ -44,8 +46,6 @@
 	struct resource *irq_res;	/* IRQ resource */
 	struct resource	*mem_res;	/* Memory resource */
 	struct mtx sc_mtx;		/* basically a perimeter lock */
-
-	int intr;
 };
 
 static inline uint32_t
@@ -170,7 +170,7 @@
 {
 	struct at91_twi_softc *sc = xsc;
 
-	sc->intr++;
+	wakeup(sc);
 }
 
 static device_method_t at91_twi_methods[] = {

==== //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#2 (text+ko) ====

@@ -42,4 +42,32 @@
 #define TWI_RHR		0x30		/* TWI Receiver Holding Register */
 #define TWI_THR		0x34		/* TWI Transmit Holding Register */
 
+/* TWI_CR */
+#define TWI_CR_START	(1U << 0)	/* Send a start */
+#define TWT_CR_STOP	(1U << 1)	/* Send a stop */
+#define TWT_CR_MSEN	(1U << 2)	/* Master Send Enable */
+#define TWT_CR_MSDIS	(1U << 3)	/* Master Send Disable */
+#define TWT_CR_SWRST	(1U << 7)	/* Software Reset */
+
+/* TWI_MMR */
+#define TWT_MMR_IADRSZ(n) ((n) << 8)	/* Set size of transfer */
+#define TWT_MMR_MREAD	(1U << 12)	/* Master Read Direction */
+#define TWT_MMR_DADR(n)	((n) << 16)	/* Device Address */
+
+/* TWI_CWGR */
+#define TWT_CWGR_CKDIV(x) ((x) << 16)	/* Clock Divider */
+#define TWT_CWGR_CHDIV(x) ((x) << 8)	/* Clock High Divider */
+#define TWT_CWGR_CLDIV(x) ((x) << 0)	/* Clock Low Divider */
+
+/* TWI_SR */
+/* TWI_IER */
+/* TWI_IDR */
+/* TWI_IMR */
+#define TWT_SR_TXCOMP	(1U << 0)	/* Transmission Completed */
+#define TWT_SR_RXRDY	(1U << 1)	/* Receive Holding Register Ready */
+#define TWT_SR_TXRDY	(1U << 2)	/* Transmit Holding Register Ready */
+#define TWT_SR_OVRE	(1U << 6)	/* Overrun error */
+#define TWT_SR_UNRE	(1U << 7)	/* Underrun Error */
+#define TWT_SR_NACK	(1U << 8)	/* Not Acknowledged */
+
 #endif /* ARM_AT91_AT91_TWIREG_H */