PERFORCE change 91787 for review

Kip Macy kmacy at FreeBSD.org
Tue Feb 14 22:19:06 PST 2006


http://perforce.freebsd.org/chv.cgi?CH=91787

Change 91787 by kmacy at kmacy_storage:sun4v_work on 2006/02/15 06:18:42

	define VAs for ASIs that take values
	initialize scratchpad registers along with globals
	load globals from scratchpad registers in traps using PSTATE_ALT
	values aren't saved back to scratchpads - and there are definitely
	possibilities for removing loads in many places

Affected files ...

.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asi.h#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#4 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/locore.S#3 edit

Differences ...

==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/asi.h#3 (text+ko) ====

@@ -115,4 +115,30 @@
 
 
 
+#define SCRATCH_REG_0                 0x00
+#define SCRATCH_REG_1                 0x08
+#define SCRATCH_REG_2                 0x10
+#define SCRATCH_REG_3                 0x18
+#define SCRATCH_REG_4                 0x20
+#define SCRATCH_REG_5                 0x28
+#define SCRATCH_REG_6                 0x30
+#define SCRATCH_REG_7                 0x38
+
+#define SCRATCH_REG_PCPU              SCRATCH_REG_0
+#define SCRATCH_REG_PCB               SCRATCH_REG_1
+#define SCRATCH_REG_PTD               SCRATCH_REG_2
+
+#define MMU_CID_P                     0x08
+#define MMU_CID_S                     0x10
+
+#define CPU_MONDO_QH                  0x3c0
+#define CPU_MONDO_QT                  0x3c8
+#define DEV_MONDO_QH                  0x3d0
+#define DEV_MONDO_QT                  0x3d8
+#define RES_ERROR_QH                  0x3e0
+#define RES_ERROR_QT                  0x3e8
+#define NRES_ERROR_QH                 0x3f0
+#define NRES_ERROR_QT                 0x3f8
+
+
 #endif /* !_MACHINE_ASI_H_ */

==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#4 (text+ko) ====

@@ -92,6 +92,13 @@
 #define	TTE_SET_REF(r1, r2, r3)		TTE_SET_BIT(r1, r2, r3, TD_REF)
 #define	TTE_SET_W(r1, r2, r3)		TTE_SET_BIT(r1, r2, r3, TD_W)
 
+#define LOAD_ALT \
+	mov	SCRATCH_REG_PCPU, %g0 ; \
+	ldxa	[%g0]ASI_SCRATCHPAD, PCPU_REG ; \
+	mov	SCRATCH_REG_PCB, %g0 ; \
+	ldxa	[%g0]ASI_SCRATCHPAD, PCB_REG
+
+	
 /*
  * Macros for spilling and filling live windows.
  *
@@ -604,7 +611,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	/*
 	 * Reload the tag access register.
@@ -761,7 +768,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	/*
 	 * Check if we actually came from the kernel.
@@ -940,7 +947,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	/*
 	 * Check if we actually came from the kernel.
@@ -1135,7 +1142,7 @@
 END(tl1_fp_disabled_1)
 
 	.macro	tl1_data_excptn
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 	ba,a	%xcc, tl1_data_excptn_trap
 	 nop
 	.align	32
@@ -1262,7 +1269,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	ldxa	[%g0 + AA_IMMU_TAR] %asi, %g2
 
@@ -1379,7 +1386,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	ldxa	[%g0 + AA_DMMU_TAR] %asi, %g2
 
@@ -1512,7 +1519,7 @@
 	/*
 	 * Switch to alternate globals.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	/*
 	 * Load the sfar, sfsr and tar.  Clear the sfsr.
@@ -1621,7 +1628,11 @@
  * data on kernel entry to the pcb.
  */
 ENTRY(tl1_spill_topcb)
-	wrpr	%g0, PSTATE_ALT, %pstate
+#ifdef notyet
+	/* XXX SUN4V_FIXME - I think this broken from a performance
+	 * standpoint
+	 */
+	LOAD_ALT
 
 	/* Free some globals for our use. */
 	dec	24, ASP_REG
@@ -1663,21 +1674,8 @@
 	inc	24, ASP_REG
 	retry
 END(tl1_spill_topcb)
+#endif
 
-	.macro	tl1_spill_bad	count
-	.rept	\count
-	sir
-	.align	128
-	.endr
-	.endm
-
-	.macro	tl1_fill_bad	count
-	.rept	\count
-	sir
-	.align	128
-	.endr
-	.endm
-
 	.macro	tl1_soft	count
 	.rept	\count
 	tl1_gen	T_SOFT | T_KERNEL
@@ -2033,11 +2031,8 @@
  * of cpu migration and using the wrong pcpup.
  */
 ENTRY(tl0_trap)
-	/*
-	 * Force kernel store order.
-	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
-
+	LOAD_ALT
+	
 	rdpr	%tstate, %l0
 	rdpr	%tpc, %l1
 	rdpr	%tnpc, %l2
@@ -2123,10 +2118,7 @@
  * void tl0_intr(u_int level, u_int mask)
  */
 ENTRY(tl0_intr)
-	/*
-	 * Force kernel store order.
-	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	rdpr	%tstate, %l0
 	rdpr	%tpc, %l1
@@ -2339,7 +2331,7 @@
 	 * Switch to alternate globals.  This frees up some registers we
 	 * can use after the restore changes our window.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	/*
 	 * Drop %pil to zero.  It must have been zero at the time of the
@@ -2491,9 +2483,8 @@
 	 * Restore the normal globals which have predefined values in the
 	 * kernel.  We clobbered them above restoring the user's globals
 	 * so this is very important.
-	 * XXX PSTATE_ALT must already be set.
 	 */
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 	mov	PCB_REG, %o0
 	mov	PCPU_REG, %o1
 	wrpr	%g0, PSTATE_NORMAL, %pstate
@@ -2626,7 +2617,7 @@
 	ldx	[%sp + SPOFF + CCFSZ + TF_G6], %g6
 	ldx	[%sp + SPOFF + CCFSZ + TF_G7], %g7
 
-1:	wrpr	%g0, PSTATE_ALT, %pstate
+1:	LOAD_ALT
 
 	andn	%l0, TSTATE_CWP_MASK, %g1
 	mov	%l1, %g2
@@ -2760,7 +2751,7 @@
 	ldx	[%sp + SPOFF + CCFSZ + TF_G4], %g4
 	ldx	[%sp + SPOFF + CCFSZ + TF_G5], %g5
 
-	wrpr	%g0, PSTATE_ALT, %pstate
+	LOAD_ALT
 
 	andn	%l0, TSTATE_CWP_MASK, %g1
 	mov	%l1, %g2

==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/locore.S#3 (text+ko) ====

@@ -105,7 +105,15 @@
 	mov	%o1, PCB_REG
 	mov	%o0, PCPU_REG
 
-	/* XXX SUN4V_FIXME need to set the scratchpad registers */
+	/*
+	 * store PCB_REG and PCPU_REG into their respective scratchpad registers
+	 * this allows us to retrieve them in the trap handlers - where we receive
+	 * a new set of globals
+	 */
+	mov	SCRATCH_REG_PCPU, %g1 
+	stxa	PCPU_REG, [%g1]ASI_SCRATCHPAD 
+	mov	SCRATCH_REG_PCB, %g1 
+	stxa	PCB_REG, [%g1]ASI_SCRATCHPAD 
 
 	retl
 	 nop


More information about the p4-projects mailing list