PERFORCE change 105377 for review
Matt Jacob
mjacob at FreeBSD.org
Wed Aug 30 23:17:35 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=105377
Change 105377 by mjacob at newisp on 2006/08/30 23:16:53
Remove ad hoc pci posting code and put it in the register write
functions where it belongs.
Some style diffs.
Some 2400 specific defines.
Affected files ...
.. //depot/projects/newisp/dev/isp/isp.c#4 edit
.. //depot/projects/newisp/dev/isp/isp_pci.c#5 edit
.. //depot/projects/newisp/dev/isp/ispreg.h#3 edit
Differences ...
==== //depot/projects/newisp/dev/isp/isp.c#4 (text+ko) ====
@@ -271,7 +271,9 @@
* or write FPM/FBM registers).
*/
if (IS_24XX(isp)) {
- ISP_WRITE(isp, BIU2400_HCCR, HCCR_CMD_PAUSE);
+ ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_HOST_INT);
+ ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
+ ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_PAUSE);
} else {
ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
}
@@ -595,15 +597,11 @@
*/
if (IS_24XX(isp)) {
ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RESET);
- val = ISP_READ(isp, BIU2400_HCCR);
ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RELEASE);
- val = ISP_READ(isp, BIU2400_HCCR);
ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RESET);
- val = ISP_READ(isp, BIU2400_HCCR);
} else {
ISP_WRITE(isp, HCCR, HCCR_CMD_RESET);
USEC_DELAY(100);
- /* Clear semaphore register (just to be sure) */
ISP_WRITE(isp, BIU_SEMA, 0);
}
@@ -4278,7 +4276,12 @@
} while (junk != iptr && ++i < 1000);
if (iptr != junk) {
- ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
+ if (IS_24XX(isp)) {
+ ISP_WRITE(isp, BIU2400_HCCR,
+ HCCR_2400_CMD_CLEAR_RISC_INT);
+ } else {
+ ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
+ }
isp_prt(isp, ISP_LOGWARN,
"Response Queue Out Pointer Unstable (%x, %x)",
iptr, junk);
@@ -4693,8 +4696,9 @@
case ASYNC_BUS_RESET:
isp->isp_sendmarker |= (1 << bus);
#ifdef ISP_TARGET_MODE
- if (isp_target_async(isp, bus, mbox))
+ if (isp_target_async(isp, bus, mbox)) {
rval = -1;
+ }
#endif
isp_async(isp, ISPASYNC_BUS_RESET, &bus);
break;
@@ -4752,8 +4756,9 @@
"timeout initiated SCSI bus reset of bus %d", bus);
isp->isp_sendmarker |= (1 << bus);
#ifdef ISP_TARGET_MODE
- if (isp_target_async(isp, bus, mbox))
+ if (isp_target_async(isp, bus, mbox)) {
rval = -1;
+ }
#endif
break;
@@ -4761,8 +4766,9 @@
isp_prt(isp, ISP_LOGINFO, "device reset on bus %d", bus);
isp->isp_sendmarker |= (1 << bus);
#ifdef ISP_TARGET_MODE
- if (isp_target_async(isp, bus, mbox))
+ if (isp_target_async(isp, bus, mbox)) {
rval = -1;
+ }
#endif
break;
@@ -4873,8 +4879,9 @@
isp_mark_portdb(isp, 1);
isp_async(isp, ISPASYNC_LIP, NULL);
#ifdef ISP_TARGET_MODE
- if (isp_target_async(isp, bus, mbox))
+ if (isp_target_async(isp, bus, mbox)) {
rval = -1;
+ }
#endif
/*
* We've had problems with data corruption occuring on
@@ -5031,8 +5038,9 @@
isp_prt(isp, ISP_LOGDEBUG3,
"fast post completion of %u", handles[i]);
}
- if (isp->isp_fpcchiwater < nh)
+ if (isp->isp_fpcchiwater < nh) {
isp->isp_fpcchiwater = nh;
+ }
} else {
isp->isp_intoasync++;
}
==== //depot/projects/newisp/dev/isp/isp_pci.c#5 (text+ko) ====
@@ -335,9 +335,7 @@
int16_t pci_poff[_NREG_BLKS];
bus_dma_tag_t dmat;
bus_dmamap_t *dmaps;
- struct callout_handle xx;
};
-static timeout_t isp_kick;
static device_method_t isp_pci_methods[] = {
@@ -999,20 +997,40 @@
cmd &= ~PCIM_CMD_INVEN;
}
- if (IS_23XX(isp)) {
- /*
- * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command.
- */
- isp->isp_touched = 1;
-
- }
-
if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
cmd &= ~PCIM_CMD_INTX_DISABLE;
}
if (IS_24XX(isp)) {
+ int reg;
+
cmd &= ~PCIM_CMD_INTX_DISABLE;
+
+ /*
+ * Is this a PCI-X card? If so, set max read byte count.
+ */
+ if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
+ uint16_t pxcmd;
+ reg += 2;
+
+ pxcmd = pci_read_config(dev, reg, 2);
+ pxcmd &= ~0xc;
+ pxcmd |= 0x8;
+ pci_write_config(dev, reg, 2, pxcmd);
+ }
+
+ /*
+ * Is this a PCI Express card? If so, set max read byte count.
+ */
+ if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
+ uint16_t pectl;
+
+ reg += 0x8;
+ pectl = pci_read_config(dev, reg, 2);
+ pectl &= ~0x7000;
+ pectl |= 0x4000;
+ pci_write_config(dev, reg, 2, pectl);
+ }
}
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
@@ -1070,6 +1088,13 @@
isp->isp_port = pci_get_function(dev);
}
+ if (IS_23XX(isp)) {
+ /*
+ * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command.
+ */
+ isp->isp_touched = 1;
+ }
+
/*
* Make sure we're in reset state.
*/
@@ -1097,9 +1122,6 @@
*/
ISP_UNLOCK(isp);
- if (IS_24XX(isp))
- pcs->xx = timeout(isp_kick, isp, hz/10);
-
return (0);
bad:
@@ -1153,30 +1175,12 @@
}
isp = (ispsoftc_t *) pcs;
ISP_LOCK(isp);
- if (IS_24XX(isp)) {
- untimeout(isp_kick, isp, pcs->xx);
- }
DISABLE_INTS(isp);
ISP_UNLOCK(isp);
return (0);
}
static void
-isp_kick(void *arg)
-{
- ispsoftc_t *isp = arg;
- struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
- uint32_t isr, sema, mbox;
-
- ISP_LOCK(isp);
- if (ISP_READ_ISR(isp, &isr, &sema, &mbox)) {
- isp_intr(isp, isr, sema, mbox);
- }
- pcs->xx = timeout(isp_kick, isp, hz/10);
- ISP_UNLOCK(isp);
-}
-
-static void
isp_pci_intr(void *arg)
{
ispsoftc_t *isp = arg;
@@ -1360,6 +1364,7 @@
*semap = 0;
return (1);
default:
+ ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
return (0);
}
@@ -1392,6 +1397,7 @@
{
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int oldconf = 0;
+ volatile int junk;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
/*
@@ -1400,10 +1406,13 @@
oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
oldconf | BIU_PCI_CONF1_SXP);
+ junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
}
BXW2(pcs, IspVirt2Off(isp, regoff), val);
+ junk = BXR2(pcs, IspVirt2Off(isp, regoff));
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
+ junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
}
}
@@ -1443,6 +1452,7 @@
{
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int oc = 0;
+ volatile int junk;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
(regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
@@ -1457,14 +1467,18 @@
else
tc |= BIU_PCI1080_CONF1_SXP0;
BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
+ junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
oc | BIU_PCI1080_CONF1_DMA);
+ junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
}
BXW2(pcs, IspVirt2Off(isp, regoff), val);
+ junk = BXR2(pcs, IspVirt2Off(isp, regoff));
if (oc) {
BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
+ junk = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
}
}
@@ -1536,12 +1550,14 @@
{
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int block = regoff & _BLK_REG_MASK;
+ volatile int junk;
switch (block) {
case BIU_BLOCK:
break;
case MBOX_BLOCK:
BXW2(pcs, IspVirt2Off(pcs, regoff), val);
+ junk = BXR2(pcs, IspVirt2Off(pcs, regoff));
return;
case SXP_BLOCK:
isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
@@ -1577,6 +1593,7 @@
case BIU2400_GPIOE:
case BIU2400_HSEMA:
BXW4(pcs, IspVirt2Off(pcs, regoff), val);
+ junk = BXR4(pcs, IspVirt2Off(pcs, regoff));
break;
default:
isp_prt(isp, ISP_LOGERR,
==== //depot/projects/newisp/dev/isp/ispreg.h#3 (text+ko) ====
@@ -239,8 +239,7 @@
ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \
(IS_24XX(isp) ? \
(ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \
- (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))); \
- (void) INTS_ENABLED(isp)
+ (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK))))
#define DISABLE_INTS(isp) \
IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0)
@@ -405,11 +404,11 @@
#define BIU2400_SOFT_RESET (1 << 0)
/* BIU2400_ICR definitions */
-#define BIU2400_ICR_ENA_RISC_INT (1 << 3)
-#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
+#define BIU2400_ICR_ENA_RISC_INT 0x8
+#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
/* BIU2400_ISR definitions */
-#define BIU2400_ISR_RISC_INT (1 << 3)
+#define BIU2400_ISR_RISC_INT 0x8
#define BIU2400_R2HST_INTR BIU_R2HST_INTR
#define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED
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