PERFORCE change 96169 for review

[Marcel Moolenaar]

http://perforce.freebsd.org/chv.cgi?CH=96169

Change 96169 by marcel at marcel_nfs on 2006/04/26 22:40:37

	Get the Interrupt Latch Register (ILR) type present on the
	card. The Quatech card has a Digi compatible ILR, except
	for the complication that the DLAB bit of the last write to
	the LCR register of *any* UART controls whether the SPR
	register functions as the ILR or the option register. The
	ILR may not be active when we get the interrupt.
	
	This does not yet add the code to actually read the ILR...

Affected files ...

.. //depot/projects/uart/dev/puc/puc.c#36 edit
.. //depot/projects/uart/dev/puc/puc_bfe.h#4 edit
.. //depot/projects/uart/dev/puc/puc_cfg.c#3 edit
.. //depot/projects/uart/dev/puc/puc_cfg.h#3 edit
.. //depot/projects/uart/dev/puc/pucdata.c#28 edit

Differences ...

==== //depot/projects/uart/dev/puc/puc.c#36 (text+ko) ====

@@ -272,6 +272,13 @@
 			device_set_ivars(port->p_dev, (void *)port);
 	}
 
+	error = puc_config(sc, PUC_CFG_GET_ILR, 0, &res);
+	if (error)
+		goto fail;
+	sc->sc_ilr = res;
+	if (bootverbose && sc->sc_ilr != 0)
+		device_printf(dev, "using interrupt latch register\n");
+
 	sc->sc_irid = 0;
 	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
 	    RF_ACTIVE|RF_SHAREABLE);

==== //depot/projects/uart/dev/puc/puc_bfe.h#4 (text+ko) ====

@@ -67,6 +67,8 @@
 	int		sc_leaving:1;
 	int		sc_polled:1;
 
+	int		sc_ilr;
+
 	/*
 	 * Bitmask of ports that use the serdev I/F. This allows for
 	 * 32 ports on ILP32 machines and 64 ports on LP64 machines.

==== //depot/projects/uart/dev/puc/puc_cfg.c#3 (text+ko) ====

@@ -55,6 +55,9 @@
 			return (error);
 		*r = cfg->clock;
 		return (0);
+	case PUC_CFG_GET_ILR:
+		*r = PUC_ILR_NONE;
+		return (0);
 	case PUC_CFG_GET_LEN:
 		/* The length of bus space needed by the port. */
 		*r = 8;

==== //depot/projects/uart/dev/puc/puc_cfg.h#3 (text+ko) ====

@@ -47,12 +47,14 @@
 #define	PUC_PORT_16S		13	/* 16 serial ports */
 
 /* Interrupt Latch Register (ILR) types */
-#define PUC_ILR_TYPE_NONE       0
-#define PUC_ILR_TYPE_DIGI       1
+#define PUC_ILR_NONE		0
+#define PUC_ILR_DIGI		1
+#define PUC_ILR_QUATECH		2
 
 /* Configuration queries. */
 enum puc_cfg_cmd {
 	PUC_CFG_GET_CLOCK,
+	PUC_CFG_GET_ILR,
 	PUC_CFG_GET_LEN,
 	PUC_CFG_GET_NPORTS,
 	PUC_CFG_GET_OFS,

==== //depot/projects/uart/dev/puc/pucdata.c#28 (text+ko) ====

@@ -800,6 +800,12 @@
 		} else
 			*res = DEFAULT_RCLK << v0;
 		return (0);
+	case PUC_CFG_GET_ILR:
+		v0 = sc->sc_cfg_data & 0xff;
+		v1 = (sc->sc_cfg_data >> 8) & 0xff;
+		*res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
+		    ? PUC_ILR_NONE : PUC_ILR_QUATECH;
+		return (0);
 	default:
 		break;
 	}