PERFORCE change 95165 for review
Warner Losh
imp at FreeBSD.org
Thu Apr 13 16:55:02 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=95165
Change 95165 by imp at imp_hammer on 2006/04/13 16:54:08
#define FOO ((unsigned int) 1234)
is bogus, since FOO can't be used in #if statements. It is
also needlessly verbose. Use
#define FOO 1234u
instead which is likely what was wanted in the first place.
Affected files ...
.. //depot/projects/arm/src/sys/boot/arm/at91/inc/AT91RM9200.h#2 edit
Differences ...
==== //depot/projects/arm/src/sys/boot/arm/at91/inc/AT91RM9200.h#2 (text) ====
@@ -321,50 +321,50 @@
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+#define AT91C_MC_RCB (0x1u << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+#define AT91C_MC_UNDADD (0x1u << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1u << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_MPU (0x1u << 2) // (MC) Memory protection Unit Abort Status
+#define AT91C_MC_ABTSZ (0x3u << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0u << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1u << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2u << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3u << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0u << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1u << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2u << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1u << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1u << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1u << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1u << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection
-#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
-#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
-#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size
-#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte
-#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte
-#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte
-#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte
-#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte
-#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte
-#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte
-#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte
-#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte
-#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte
-#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte
-#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte
-#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte
-#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte
-#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte
-#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte
-#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
+#define AT91C_MC_PROT (0x3u << 0) // (MC) Protection
+#define AT91C_MC_PROT_PNAUNA 0x0u // (MC) Privilege: No Access, User: No Access
+#define AT91C_MC_PROT_PRWUNA 0x1u // (MC) Privilege: Read/Write, User: No Access
+#define AT91C_MC_PROT_PRWURO 0x2u // (MC) Privilege: Read/Write, User: Read Only
+#define AT91C_MC_PROT_PRWURW 0x3u // (MC) Privilege: Read/Write, User: Read/Write
+#define AT91C_MC_SIZE (0xFu << 4) // (MC) Internal Area Size
+#define AT91C_MC_SIZE_1KB (0x0u << 4) // (MC) Area size 1KByte
+#define AT91C_MC_SIZE_2KB (0x1u << 4) // (MC) Area size 2KByte
+#define AT91C_MC_SIZE_4KB (0x2u << 4) // (MC) Area size 4KByte
+#define AT91C_MC_SIZE_8KB (0x3u << 4) // (MC) Area size 8KByte
+#define AT91C_MC_SIZE_16KB (0x4u << 4) // (MC) Area size 16KByte
+#define AT91C_MC_SIZE_32KB (0x5u << 4) // (MC) Area size 32KByte
+#define AT91C_MC_SIZE_64KB (0x6u << 4) // (MC) Area size 64KByte
+#define AT91C_MC_SIZE_128KB (0x7u << 4) // (MC) Area size 128KByte
+#define AT91C_MC_SIZE_256KB (0x8u << 4) // (MC) Area size 256KByte
+#define AT91C_MC_SIZE_512KB (0x9u << 4) // (MC) Area size 512KByte
+#define AT91C_MC_SIZE_1MB (0xAu << 4) // (MC) Area size 1MByte
+#define AT91C_MC_SIZE_2MB (0xBu << 4) // (MC) Area size 2MByte
+#define AT91C_MC_SIZE_4MB (0xCu << 4) // (MC) Area size 4MByte
+#define AT91C_MC_SIZE_8MB (0xDu << 4) // (MC) Area size 8MByte
+#define AT91C_MC_SIZE_16MB (0xEu << 4) // (MC) Area size 16MByte
+#define AT91C_MC_SIZE_64MB (0xFu << 4) // (MC) Area size 64MByte
+#define AT91C_MC_BA (0x3FFFFu << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit
+#define AT91C_MC_PUEB (0x1u << 0) // (MC) Protection Unit enable Bit
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface
@@ -385,52 +385,52 @@
} AT91S_RTC, *AT91PS_RTC;
// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------
-#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register
-#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register
-#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection
-#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change.
-#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change.
-#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight.
-#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon.
-#define AT91C_RTC_CALEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection
-#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
-#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
-#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
+#define AT91C_RTC_UPDTIM (0x1u << 0) // (RTC) Update Request Time Register
+#define AT91C_RTC_UPDCAL (0x1u << 1) // (RTC) Update Request Calendar Register
+#define AT91C_RTC_TIMEVSEL (0x3u << 8) // (RTC) Time Event Selection
+#define AT91C_RTC_TIMEVSEL_MINUTE (0x0u << 8) // (RTC) Minute change.
+#define AT91C_RTC_TIMEVSEL_HOUR (0x1u << 8) // (RTC) Hour change.
+#define AT91C_RTC_TIMEVSEL_DAY24 (0x2u << 8) // (RTC) Every day at midnight.
+#define AT91C_RTC_TIMEVSEL_DAY12 (0x3u << 8) // (RTC) Every day at noon.
+#define AT91C_RTC_CALEVSEL (0x3u << 16) // (RTC) Calendar Event Selection
+#define AT91C_RTC_CALEVSEL_WEEK (0x0u << 16) // (RTC) Week change (every Monday at time 00:00:00).
+#define AT91C_RTC_CALEVSEL_MONTH (0x1u << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
+#define AT91C_RTC_CALEVSEL_YEAR (0x2u << 16) // (RTC) Year change (every January 1 at time 00:00:00).
// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------
-#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode
+#define AT91C_RTC_HRMOD (0x1u << 0) // (RTC) 12-24 hour Mode
// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
-#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second
-#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute
-#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour
-#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
+#define AT91C_RTC_SEC (0x7Fu << 0) // (RTC) Current Second
+#define AT91C_RTC_MIN (0x7Fu << 8) // (RTC) Current Minute
+#define AT91C_RTC_HOUR (0x1Fu << 16) // (RTC) Current Hour
+#define AT91C_RTC_AMPM (0x1u << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
-#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century
-#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year
-#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month
-#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day
-#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date
+#define AT91C_RTC_CENT (0x3Fu << 0) // (RTC) Current Century
+#define AT91C_RTC_YEAR (0xFFu << 8) // (RTC) Current Year
+#define AT91C_RTC_MONTH (0x1Fu << 16) // (RTC) Current Month
+#define AT91C_RTC_DAY (0x7u << 21) // (RTC) Current Day
+#define AT91C_RTC_DATE (0x3Fu << 24) // (RTC) Current Date
// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------
-#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable
-#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm
-#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour
+#define AT91C_RTC_SECEN (0x1u << 7) // (RTC) Second Alarm Enable
+#define AT91C_RTC_MINEN (0x1u << 15) // (RTC) Minute Alarm
+#define AT91C_RTC_HOUREN (0x1u << 23) // (RTC) Current Hour
// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------
-#define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable
-#define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable
+#define AT91C_RTC_MONTHEN (0x1u << 23) // (RTC) Month Alarm Enable
+#define AT91C_RTC_DATEEN (0x1u << 31) // (RTC) Date Alarm Enable
// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------
-#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update
-#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag
-#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event
-#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event
-#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event
+#define AT91C_RTC_ACKUPD (0x1u << 0) // (RTC) Acknowledge for Update
+#define AT91C_RTC_ALARM (0x1u << 1) // (RTC) Alarm Flag
+#define AT91C_RTC_SECEV (0x1u << 2) // (RTC) Second Event
+#define AT91C_RTC_TIMEV (0x1u << 3) // (RTC) Time Event
+#define AT91C_RTC_CALEV (0x1u << 4) // (RTC) Calendar event
// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------
// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------
// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------
// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------
// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------
-#define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time
-#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar
-#define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm
-#define AT91C_RTC_NVCALALR ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm
+#define AT91C_RTC_NVTIM (0x1u << 0) // (RTC) Non valid Time
+#define AT91C_RTC_NVCAL (0x1u << 1) // (RTC) Non valid Calendar
+#define AT91C_RTC_NVTIMALR (0x1u << 2) // (RTC) Non valid time Alarm
+#define AT91C_RTC_NVCALALR (0x1u << 3) // (RTC) Nonvalid Calendar Alarm
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Timer Interface
@@ -449,27 +449,27 @@
} AT91S_ST, *AT91PS_ST;
// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------
-#define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart
+#define AT91C_ST_WDRST (0x1u << 0) // (ST) Watchdog Timer Restart
// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------
-#define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart
+#define AT91C_ST_PIV (0xFFFFu << 0) // (ST) Watchdog Timer Restart
// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------
-#define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart
-#define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable
-#define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable
+#define AT91C_ST_WDV (0xFFFFu << 0) // (ST) Watchdog Timer Restart
+#define AT91C_ST_RSTEN (0x1u << 16) // (ST) Reset Enable
+#define AT91C_ST_EXTEN (0x1u << 17) // (ST) External Signal Assertion Enable
// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------
-#define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value
+#define AT91C_ST_RTPRES (0xFFFFu << 0) // (ST) Real-time Timer Prescaler Value
// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------
-#define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt
-#define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow
-#define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment
-#define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status
+#define AT91C_ST_PITS (0x1u << 0) // (ST) Period Interval Timer Interrupt
+#define AT91C_ST_WDOVF (0x1u << 1) // (ST) Watchdog Overflow
+#define AT91C_ST_RTTINC (0x1u << 2) // (ST) Real-time Timer Increment
+#define AT91C_ST_ALMS (0x1u << 3) // (ST) Alarm Status
// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------
// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------
// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------
// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------
-#define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value
+#define AT91C_ST_ALMV (0xFFFFFu << 0) // (ST) Alarm Value Value
// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------
-#define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value
+#define AT91C_ST_CRTV (0xFFFFFu << 0) // (ST) Current Real-time Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
@@ -493,53 +493,53 @@
} AT91S_PMC, *AT91PS_PMC;
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock
-#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
-#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK (0x1u << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1u << 1) // (PMC) USB Device Port Clock
+#define AT91C_PMC_MCKUDP (0x1u << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
+#define AT91C_PMC_UHP (0x1u << 4) // (PMC) USB Host Port Clock
+#define AT91C_PMC_PCK0 (0x1u << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1u << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1u << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1u << 11) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK4 (0x1u << 12) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK5 (0x1u << 13) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK6 (0x1u << 14) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK7 (0x1u << 15) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
-#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
-#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division
-#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same
-#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
-#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock
-#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock
+#define AT91C_PMC_CSS (0x3u << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK 0x0u // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK 0x1u // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLLA_CLK 0x2u // (PMC) Clock from PLL A is selected
+#define AT91C_PMC_CSS_PLLB_CLK 0x3u // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES (0x7u << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0u << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1u << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2u << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3u << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4u << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5u << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6u << 2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV (0x3u << 8) // (PMC) Master Clock Division
+#define AT91C_PMC_MDIV_1 (0x0u << 8) // (PMC) The master clock and the processor clock are the same
+#define AT91C_PMC_MDIV_2 (0x1u << 8) // (PMC) The processor clock is twice as fast as the master clock
+#define AT91C_PMC_MDIV_3 (0x2u << 8) // (PMC) The processor clock is three times faster than the master clock
+#define AT91C_PMC_MDIV_4 (0x3u << 8) // (PMC) The processor clock is four times faster than the master clock
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_MOSCS (0x1u << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA (0x1u << 1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB (0x1u << 2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1u << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1u << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1u << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1u << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1u << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK4RDY (0x1u << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK5RDY (0x1u << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK6RDY (0x1u << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK7RDY (0x1u << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
@@ -555,37 +555,37 @@
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+#define AT91C_CKGR_MOSCEN (0x1u << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCTEST (0x1u << 1) // (CKGR) Oscillator Test
+#define AT91C_CKGR_OSCOUNT (0xFFu << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+#define AT91C_CKGR_MAINF (0xFFFFu << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1u << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
-#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter
-#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range
-#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier
-#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source
+#define AT91C_CKGR_DIVA (0xFFu << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIVA_0 0x0u // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIVA_BYPASS 0x1u // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLACOUNT (0x3Fu << 8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA (0x3u << 14) // (CKGR) PLL A Output Frequency Range
+#define AT91C_CKGR_OUTA_0 (0x0u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_1 (0x1u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_2 (0x2u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_3 (0x3u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA (0x7FFu << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA (0x1u << 29) // (CKGR) PLL A Source
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter
-#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range
-#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier
-#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports
-#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use
+#define AT91C_CKGR_DIVB (0xFFu << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIVB_0 0x0u // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIVB_BYPASS 0x1u // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLBCOUNT (0x3Fu << 8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB (0x3u << 14) // (CKGR) PLL B Output Frequency Range
+#define AT91C_CKGR_OUTB_0 (0x0u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_1 (0x1u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_2 (0x2u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_3 (0x3u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB (0x7FFu << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USB_96M (0x1u << 28) // (CKGR) Divider for USB Ports
+#define AT91C_CKGR_USB_PLL (0x1u << 29) // (CKGR) PLL Use
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
@@ -660,43 +660,43 @@
} AT91S_DBGU, *AT91PS_DBGU;
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTRX (0x1u << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1u << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1u << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1u << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1u << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1u << 7) // (DBGU) Transmitter Disable
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+#define AT91C_US_PAR (0x7u << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0u << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1u << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2u << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3u << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4u << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6u << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3u << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0u << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1u << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2u << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3u << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+#define AT91C_US_RXRDY (0x1u << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1u << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1u << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1u << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1u << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1u << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1u << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1u << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1u << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1u << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1u << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1u << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
+#define AT91C_US_FORCE_NTRST (0x1u << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
@@ -715,10 +715,10 @@
} AT91S_PDC, *AT91PS_PDC;
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+#define AT91C_PDC_RXTEN (0x1u << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1u << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1u << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1u << 9) // (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
// *****************************************************************************
@@ -748,20 +748,20 @@
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+#define AT91C_AIC_PRIOR (0x7u << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST 0x0u // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST 0x7u // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3u << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+#define AT91C_AIC_NFIQ (0x1u << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1u << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
+#define AT91C_AIC_DCR_PROT (0x1u << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1u << 1) // (AIC) General Mask
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Serial Parallel Interface
@@ -791,55 +791,55 @@
} AT91S_SPI, *AT91PS_SPI;
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_SPIEN (0x1u << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1u << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1u << 7) // (SPI) SPI Software reset
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+#define AT91C_SPI_MSTR (0x1u << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1u << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0u << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1u << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1u << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_DIV32 (0x1u << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1u << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1u << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xFu << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFFu << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+#define AT91C_SPI_RD (0xFFFFu << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+#define AT91C_SPI_TD (0xFFFFu << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+#define AT91C_SPI_RDRF (0x1u << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1u << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1u << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1u << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_SPENDRX (0x1u << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_SPENDTX (0x1u << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1u << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1u << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_SPIENS (0x1u << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+#define AT91C_SPI_CPOL (0x1u << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1u << 1) // (SPI) Clock Phase
+#define AT91C_SPI_BITS (0xFu << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0u << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1u << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2u << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3u << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4u << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5u << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6u << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7u << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8u << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFFu << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFFu << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT (0xFFu << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
@@ -877,72 +877,72 @@
} AT91S_SSC, *AT91PS_SSC;
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+#define AT91C_SSC_RXEN (0x1u << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1u << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1u << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1u << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1u << 15) // (SSC) Software Reset
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
-#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+#define AT91C_SSC_CKS (0x3u << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV 0x0u // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK 0x1u // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK 0x2u // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7u << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0u << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1u << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2u << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1u << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG (0x3u << 6) // (SSC) Receive/Transmit Clock Gating Selection
+#define AT91C_SSC_CKG_NONE (0x0u << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define AT91C_SSC_CKG_LOW (0x1u << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define AT91C_SSC_CKG_HIGH (0x2u << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START (0xFu << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0u << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1u << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2u << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3u << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4u << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5u << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6u << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7u << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8u << 8) // (SSC) Compare 0
+#define AT91C_SSC_STOP (0x1u << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT (0x1u << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY (0xFFu << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFFu << 24) // (SSC) Receive/Transmit Period Divider Selection
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+#define AT91C_SSC_DATLEN (0x1Fu << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1u << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1u << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xFu << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xFu << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7u << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1u << 24) // (SSC) Frame Sync Edge Detection
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+#define AT91C_SSC_DATDEF (0x1u << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1u << 23) // (SSC) Frame Sync Data Enable
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
-#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+#define AT91C_SSC_TXRDY (0x1u << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1u << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1u << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1u << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1u << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1u << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1u << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1u << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0 (0x1u << 8) // (SSC) Compare 0
+#define AT91C_SSC_CP1 (0x1u << 9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN (0x1u << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1u << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1u << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1u << 17) // (SSC) Receive Enable
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
@@ -981,67 +981,67 @@
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+#define AT91C_US_RSTSTA (0x1u << 8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK (0x1u << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1u << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1u << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1u << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1u << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1u << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1u << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1u << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1u << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1u << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1u << 19) // (USART) Request to Send Disable
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+#define AT91C_US_USMODE (0xFu << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL 0x0u // (USART) Normal
+#define AT91C_US_USMODE_RS485 0x1u // (USART) RS485
+#define AT91C_US_USMODE_HWHSH 0x2u // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM 0x3u // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 0x4u // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 0x6u // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA 0x8u // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH 0xCu // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3u << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0u << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1u << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2u << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3u << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3u << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0u << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1u << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2u << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3u << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1u << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3u << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0u << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1u << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2u << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1u << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1u << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1u << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1u << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1u << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1u << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1u << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1u << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+#define AT91C_US_RXBRK (0x1u << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1u << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1u << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1u << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1u << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1u << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1u << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1u << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+#define AT91C_US_RI (0x1u << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1u << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1u << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1u << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
@@ -1062,38 +1062,38 @@
} AT91S_TWI, *AT91PS_TWI;
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+#define AT91C_TWI_START (0x1u << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1u << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1u << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1u << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN (0x1u << 4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS (0x1u << 5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST (0x1u << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+#define AT91C_TWI_IADRSZ (0x3u << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0u << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1u << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2u << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3u << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1u << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7Fu << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
-#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
+#define AT91C_TWI_SADR (0x7Fu << 16) // (TWI) Slave Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+#define AT91C_TWI_CLDIV (0xFFu << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFFu << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7u << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost
+#define AT91C_TWI_TXCOMP (0x1u << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1u << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1u << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD (0x1u << 3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC (0x1u << 4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC (0x1u << 5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE (0x1u << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1u << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1u << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST (0x1u << 9) // (TWI) Arbitration Lost
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
@@ -1131,73 +1131,73 @@
} AT91S_MCI, *AT91PS_MCI;
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
-#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable
-#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable
-#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable
-#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable
+#define AT91C_MCI_MCIEN (0x1u << 0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS (0x1u << 1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN (0x1u << 2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS (0x1u << 3) // (MCI) Power Save Mode Disable
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
-#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider
-#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider
-#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value
-#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode
-#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length
+#define AT91C_MCI_CLKDIV (0x1u << 0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV (0x1u << 8) // (MCI) Power Saving Divider
+#define AT91C_MCI_PDCPADV (0x1u << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE (0x1u << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN (0x1u << 18) // (MCI) Data Block Length
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
-#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number
-#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier
-#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1
-#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16
-#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128
-#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256
-#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024
-#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096
-#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536
-#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576
+#define AT91C_MCI_DTOCYC (0x1u << 0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL (0x7u << 4) // (MCI) Data Timeout Multiplier
+#define AT91C_MCI_DTOMUL_1 (0x0u << 4) // (MCI) DTOCYC x 1
+#define AT91C_MCI_DTOMUL_16 (0x1u << 4) // (MCI) DTOCYC x 16
+#define AT91C_MCI_DTOMUL_128 (0x2u << 4) // (MCI) DTOCYC x 128
+#define AT91C_MCI_DTOMUL_256 (0x3u << 4) // (MCI) DTOCYC x 256
+#define AT91C_MCI_DTOMUL_1024 (0x4u << 4) // (MCI) DTOCYC x 1024
+#define AT91C_MCI_DTOMUL_4096 (0x5u << 4) // (MCI) DTOCYC x 4096
+#define AT91C_MCI_DTOMUL_65536 (0x6u << 4) // (MCI) DTOCYC x 65536
+#define AT91C_MCI_DTOMUL_1048576 (0x7u << 4) // (MCI) DTOCYC x 1048576
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
-#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector
-#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width
+#define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
-#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type
-#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response
-#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response
-#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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