PERFORCE change 94999 for review

Warner Losh imp at FreeBSD.org
Tue Apr 11 17:23:39 UTC 2006


http://perforce.freebsd.org/chv.cgi?CH=94999

Change 94999 by imp at imp_hammer on 2006/04/11 17:23:09

	Make it possible to compile for TSC board or KB920x board.  Turns
	out we can't probe the SDRAM bus size, so back off from auto
	clock detection.  I think these changes save 8 bytes.

Affected files ...

.. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/Makefile#5 edit
.. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#10 edit
.. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.h#4 edit

Differences ...

==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/Makefile#5 (text+ko) ====

@@ -2,7 +2,7 @@
 SRCS=arm_init.s at91rm9200_lowlevel.c lib.c main.c xmodem.c
 NO_MAN=
 LDFLAGS=-e 0 -T linker.cfg
-CFLAGS=-O2 -mcpu=arm9 -ffreestanding
+CFLAGS=-O2 -mcpu=arm9 -ffreestanding -DBOOT0_TSC
 OBJS+=  ${SRCS:N*.h:R:S/$/.o/g}
 CLEANFILES=${OBJS} ${PROG} ${PROG}.out
 

==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#10 (text+ko) ====

@@ -28,9 +28,6 @@
 
 #define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_CLOCK)
 
-//#define SDRAM_WIDTH	AT91C_SDRC_DBW_16_BITS
-#define SDRAM_WIDTH	AT91C_SDRC_DBW_32_BITS
-
 /*
  * .KB_C_FN_DEFINITION_START
  * void DefaultSystemInit(void)
@@ -46,7 +43,6 @@
 	register unsigned	value;
 	int i;
 	volatile unsigned short *p = (unsigned short *)SDRAM_BASE;
-	unsigned int div;
 
 	AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10;
 	AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10;
@@ -57,20 +53,12 @@
 	//    main osc = 10Mhz
 	//    PLLB configured for 96MHz (48MHz after div)
 	//    CSS = PLLB
-	
-	// Crude selection between 16MHz clock and 10MHz clock.
-//	if (AT91C_BASE_CKGR->CKGR_MCFR & AT91C_CKGR_MAINF < 6000)
-//		div = OSC_MAIN_FREQ_DIV_10;
-//	else
-		div = OSC_MAIN_FREQ_DIV_16;
-	
 	// set PLLA = 180MHz
 	// assume main osc = 10Mhz
 	// div = 5 , out = 2 (150MHz = 240MHz)
 	value = AT91C_BASE_CKGR->CKGR_PLLAR;
-	value &= ~AT91C_CKGR_DIVA;
-	value &= ~AT91C_CKGR_OUTA;
-	value |= div | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA;
+	value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA);
+	value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA;
 	AT91C_BASE_CKGR->CKGR_PLLAR = value;
 
 	// mul = 90
@@ -80,18 +68,18 @@
 	AT91C_BASE_CKGR->CKGR_PLLAR = value;
 
 	// wait for lock
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)) ;
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA))
+		continue;
 
 	// change divider = 3, pres = 1
 	value = AT91C_BASE_PMC->PMC_MCKR;
-	value &= ~AT91C_PMC_MDIV;
-	value |= AT91C_PMC_MDIV_3;
-	value &= ~AT91C_PMC_PRES;
-	value |= AT91C_PMC_PRES_CLK;
+	value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES);
+	value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK;
 	AT91C_BASE_PMC->PMC_MCKR = value;
 
 	// wait for update
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) ;
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
+		continue;
 
 	// change CSS = PLLA
 	value &= ~AT91C_PMC_CSS;
@@ -99,7 +87,8 @@
 	AT91C_BASE_PMC->PMC_MCKR = value;
 
 	// wait for update
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) ;
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
+		continue;
 
 	// setup SDRAM access
 	// EBI chip-select register (CS1 = SDRAM controller)

==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.h#4 (text+ko) ====

@@ -29,9 +29,18 @@
 
 #define SDRAM_BASE		0x20000000
 
+#ifdef BOOT0_KB9202
 /* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
-#define OSC_MAIN_FREQ_DIV_10	5	/* for 10MHz osc */
-#define OSC_MAIN_FREQ_DIV_16	8	/* for 16MHz osc */
+#define OSC_MAIN_FREQ_DIV	5	/* for 10MHz osc */
+#define SDRAM_WIDTH	AT91C_SDRC_DBW_16_BITS
+#endif
+
+#ifdef BOOT0_TSC
+/* The following divisor sets PLLA frequency: e.g. 16/8 * 90 = 180MHz */
+#define OSC_MAIN_FREQ_DIV	8	/* for 16MHz osc */
+#define SDRAM_WIDTH	AT91C_SDRC_DBW_32_BITS
+#endif
+
 #define OSC_MAIN_MULT		90	/* Constant for both */
 
 /* Master clock frequency at power-up */


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