PERFORCE change 71412 for review

[Olivier Houchard]

http://perforce.freebsd.org/chv.cgi?CH=71412

Change 71412 by cognet at cognet on 2005/02/20 21:24:07

	Bring back a more generic locore.S. Also fix the braindead attempt
	to get the pc to our virtual space. in ts7200_machdep.c, move the
	call to cninit() after the new page table is used, since the uart
	memio is not mapped anymore in locore.S

Affected files ...

.. //depot/projects/arm/src/sys/arm/arm/locore.S#4 edit
.. //depot/projects/arm/src/sys/arm/ep93xx/ts7200_machdep.c#4 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/arm/locore.S#4 (text+ko) ====

@@ -1,6 +1,8 @@
+<<<<<<< locore.S
+=======
 /*	$NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $	*/
 
-/*-
+/*
  * Copyright (C) 1994-1997 Mark Brinicombe
  * Copyright (C) 1994 Brini
  * All rights reserved.
@@ -37,7 +39,7 @@
 #include <machine/asm.h>
 #include <machine/armreg.h>
 #include <machine/pte.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/locore.S,v 1.8 2005/01/23 22:08:31 cognet Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/locore.S,v 1.4 2004/09/28 14:37:08 cognet Exp $");
 
 /* What size should this really be ? It is only used by init_arm() */
 #define INIT_ARM_STACK_SIZE	2048
@@ -129,10 +131,7 @@
 3:	
 	ldmia	r4!, {r1,r2,r3}   /* # of sections, PA|attr, VA */
 	cmp	r1, #0
-	adrne	r5, 2b
-	bicne	r5, r5, #0xff000000
-	orrne	r5, r5, #PHYSADDR
-	movne	pc, r5
+	bne	2b	
 
 	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
 	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
@@ -160,20 +159,6 @@
 	subs	r2, r2, #4
 	bgt	.L1
 
-	/* fix up the pc to be at KERNVIRTADDR */
-	ldr	r4, =KERNVIRTADDR
-	cmp	pc, r4
-#if	KERNVIRTADDR > KERNPHYSADDR
-	ldr	r4, =KERNVIRTADDR
-	ldr	r5, =KERNPHYSADDR
-	sub	r4, r4, r5
-	add	pc, pc, r4
-#else
-	ldrgt	r4, =KERNPHYSADDR
-	ldrgt	r5, =KERNVIRTADDR
-	subgt	r4, r4, r5
-	sublt	pc, pc, r4
-#endif
 	ldr	fp, =KERNVIRTADDR	/* trace back starts here */
 	bl	_C_LABEL(initarm)	/* Off we go */
 
@@ -195,11 +180,12 @@
 	.word	STARTUP_PAGETABLE_ADDR
 mmu_init_table:	
 	/* fill all table VA==PA */
+	MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
 	/* map SDRAM VA==PA, WT cacheable */
 	MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
 	/* map VA 0xc0000000..0xc3ffffff to PA */
 	MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
-	MMU_INIT(0xf0100000, 0x80800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
+	MMU_INIT(0xfe800000, 0xfe800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
 
 	.word 0	/* end of table */
 #endif
@@ -314,23 +300,18 @@
 	mov	pc, r7
 #endif
 
-ENTRY(asm_putc)
-	ldr r1, =0xf01c0000
-	strb r0, [r1]
-	mov pc, lr
-
 /*
  * setjump + longjmp
  */
 ENTRY(setjmp)
 	stmia	r0, {r4-r14}
 	mov	r0, #0x00000000
-	RET
+	mov	pc, lr
 
 ENTRY(longjmp)
 	ldmia	r0, {r4-r14}
 	mov	r0, #0x00000001
-	RET
+	mov	pc, lr
 
 	.data
 	.global _C_LABEL(esym)
@@ -357,3 +338,4 @@
 szsigcode:
 	.long esigcode-sigcode
 /* End of locore.S */
+>>>>>>> 1.4

==== //depot/projects/arm/src/sys/arm/ep93xx/ts7200_machdep.c#4 (text+ko) ====

@@ -221,7 +221,6 @@
 	boothowto |= RB_VERBOSE | RB_SINGLE;
 	i = 0;
 	set_cpufuncs();
-	cninit();
 
 	fake_preload[i++] = MODINFO_NAME;
 	fake_preload[i++] = strlen("elf kernel") + 1;
@@ -395,6 +394,7 @@
 	cpu_tlb_flushID();
 
 	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+	cninit();
 
 	/*
 	 * Pages were allocated during the secondary bootstrap for the