PERFORCE change 52729 for review
Peter Wemm
peter at FreeBSD.org
Wed May 12 16:09:18 PDT 2004
http://perforce.freebsd.org/chv.cgi?CH=52729
Change 52729 by peter at peter_overcee on 2004/05/12 16:08:35
Integ -I -b i386_hammer (untested.. argh)
Affected files ...
.. //depot/projects/hammer/sys/amd64/acpica/madt.c#31 integrate
.. //depot/projects/hammer/sys/amd64/amd64/fpu.c#13 integrate
.. //depot/projects/hammer/sys/amd64/amd64/io_apic.c#24 integrate
.. //depot/projects/hammer/sys/amd64/amd64/machdep.c#84 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mptable.c#24 integrate
.. //depot/projects/hammer/sys/amd64/include/apicvar.h#21 integrate
.. //depot/projects/hammer/sys/amd64/isa/atpic.c#39 integrate
.. //depot/projects/hammer/sys/amd64/isa/atpic_vector.S#17 integrate
.. //depot/projects/hammer/sys/amd64/isa/clock.c#22 integrate
.. //depot/projects/hammer/sys/amd64/isa/icu.h#20 integrate
Differences ...
==== //depot/projects/hammer/sys/amd64/acpica/madt.c#31 (text+ko) ====
@@ -49,6 +49,7 @@
#include <machine/specialreg.h>
#include "acpi.h"
+#include <contrib/dev/acpica/actables.h>
#include <dev/acpica/acpivar.h>
#include <dev/pci/pcivar.h>
@@ -158,6 +159,7 @@
{
ACPI_TABLE_HEADER *header;
vm_offset_t length;
+ void *table;
header = madt_map(pa, offset, sizeof(ACPI_TABLE_HEADER));
if (strncmp(header->Signature, sig, 4) != 0) {
@@ -166,7 +168,14 @@
}
length = header->Length;
madt_unmap(header, sizeof(ACPI_TABLE_HEADER));
- return (madt_map(pa, offset, length));
+ table = madt_map(pa, offset, length);
+ if (ACPI_FAILURE(AcpiTbVerifyTableChecksum(table))) {
+ if (bootverbose)
+ printf("MADT: Failed checksum for table %s\n", sig);
+ madt_unmap(table, length);
+ return (NULL);
+ }
+ return (table);
}
static void
@@ -216,6 +225,16 @@
* Page 0 is used to map in the headers of candidate ACPI tables.
*/
if (rsdp->Revision >= 2) {
+ /*
+ * AcpiOsGetRootPointer only verifies the checksum for
+ * the version 1.0 portion of the RSDP. Version 2.0 has
+ * an additional checksum that we verify first.
+ */
+ if (AcpiTbChecksum(rsdp, ACPI_RSDP_XCHECKSUM_LENGTH) != 0) {
+ if (bootverbose)
+ printf("MADT: RSDP failed extended checksum\n");
+ return (ENXIO);
+ }
xsdt = madt_map_table(rsdp->XsdtPhysicalAddress, 1, XSDT_SIG);
if (xsdt == NULL) {
if (bootverbose)
@@ -252,6 +271,16 @@
printf("MADT: Found table at 0x%jx\n",
(uintmax_t)madt_physaddr);
+ /*
+ * Verify that we can map the full table and that its checksum is
+ * correct, etc.
+ */
+ madt = madt_map_table(madt_physaddr, 0, APIC_SIG);
+ if (madt == NULL)
+ return (ENXIO);
+ madt_unmap_table(madt);
+ madt = NULL;
+
return (0);
}
@@ -274,7 +303,6 @@
printf("Table '%.4s' at 0x%jx\n", table->Signature,
(uintmax_t)address);
- /* XXX: Verify checksum? */
if (strncmp(table->Signature, APIC_SIG, 4) != 0) {
madt_unmap(table, sizeof(ACPI_TABLE_HEADER));
return (0);
@@ -340,6 +368,8 @@
}
/* First, we run through adding I/O APIC's. */
+ if (madt->PCATCompat)
+ ioapic_enable_mixed_mode();
madt_walk_table(madt_parse_apics, NULL);
/* Second, we run through the table tweaking interrupt sources. */
@@ -466,10 +496,10 @@
}
/*
- * Determine properties of an interrupt source. Note that for ACPI,
- * these are only used for ISA interrupts, so we assume ISA bus values
+ * Determine properties of an interrupt source. Note that for ACPI these
+ * functions are only used for ISA interrupts, so we assume ISA bus values
* (Active Hi, Edge Triggered) for conforming values except for the ACPI
- * SCI for which we use Active Lo, Level Triggered..
+ * SCI for which we use Active Lo, Level Triggered.
*/
static enum intr_polarity
interrupt_polarity(UINT16 Polarity, UINT8 Source)
==== //depot/projects/hammer/sys/amd64/amd64/fpu.c#13 (text+ko) ====
==== //depot/projects/hammer/sys/amd64/amd64/io_apic.c#24 (text+ko) ====
@@ -51,10 +51,6 @@
#include <machine/apicvar.h>
#include <machine/segments.h>
-#if defined(DEV_ISA) && defined(DEV_ATPIC) && !defined(NO_MIXED_MODE)
-#define MIXED_MODE
-#endif
-
#define IOAPIC_ISA_INTS 16
#define IOAPIC_MEM_REGION 32
#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
@@ -117,9 +113,6 @@
struct ioapic_intsrc io_pins[0];
};
-static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
-static u_int next_id, program_logical_dest;
-
static u_int ioapic_read(volatile ioapic_t *apic, int reg);
static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
static void ioapic_enable_source(struct intsrc *isrc);
@@ -133,17 +126,23 @@
static void ioapic_suspend(struct intsrc *isrc);
static void ioapic_resume(struct intsrc *isrc);
static void ioapic_program_destination(struct ioapic_intsrc *intpin);
-#ifdef MIXED_MODE
static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
-#endif
+static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
ioapic_eoi_source, ioapic_enable_intr,
ioapic_vector, ioapic_source_pending,
ioapic_suspend, ioapic_resume,
ioapic_config_intr };
-static int next_ioapic_base, logical_clusters, current_cluster;
+static int current_cluster, logical_clusters, next_ioapic_base;
+static u_int mixed_mode_enabled, next_id, program_logical_dest;
+#if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC)
+static int mixed_mode_active = 0;
+#else
+static int mixed_mode_active = 1;
+#endif
+TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
static u_int
ioapic_read(volatile ioapic_t *apic, int reg)
@@ -344,6 +343,17 @@
}
/*
+ * APIC enumerators call this function to indicate that the 8259A AT PICs
+ * are available and that mixed mode can be used.
+ */
+void
+ioapic_enable_mixed_mode(void)
+{
+
+ mixed_mode_enabled = 1;
+}
+
+/*
* Allocate and return a logical cluster ID. Note that the first time
* this is called, it returns cluster 0. ioapic_enable_intr() treats
* the two cases of logical_clusters == 0 and logical_clusters == 1 the
@@ -418,14 +428,17 @@
* Assume that pin 0 on the first IO APIC is an ExtINT pin by
* default. Assume that intpins 1-15 are ISA interrupts and
* use suitable defaults for those. Assume that all other
- * intpins are PCI interrupts. Enable the ExtINT pin by
- * default but mask all other pins.
+ * intpins are PCI interrupts. Enable the ExtINT pin if
+ * mixed mode is available and active but mask all other pins.
*/
if (intpin->io_vector == 0) {
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
intpin->io_vector = VECTOR_EXTINT;
- intpin->io_masked = 0;
+ if (mixed_mode_enabled && mixed_mode_active)
+ intpin->io_masked = 0;
+ else
+ intpin->io_masked = 1;
} else if (intpin->io_vector < IOAPIC_ISA_INTS) {
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
@@ -670,12 +683,15 @@
ioapic_write(apic, IOAPIC_REDTBL_HI(i), flags);
mtx_unlock_spin(&icu_lock);
if (pin->io_vector < NUM_IO_INTS) {
-#ifdef MIXED_MODE
- /* Route IRQ0 via the 8259A using mixed mode. */
- if (pin->io_vector == 0)
+
+ /*
+ * Route IRQ0 via the 8259A using mixed mode if
+ * mixed mode is available and turned on.
+ */
+ if (pin->io_vector == 0 && mixed_mode_active &&
+ mixed_mode_enabled)
ioapic_setup_mixed_mode(pin);
else
-#endif
intr_register_source(&pin->io_intsrc);
}
@@ -702,7 +718,6 @@
SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
ioapic_set_logical_destinations, NULL)
-#ifdef MIXED_MODE
/*
* Support for mixed-mode interrupt sources. These sources route an ISA
* IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
@@ -711,7 +726,7 @@
* that IRQ instead.
*/
-void
+static void
ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
{
struct ioapic_intsrc *extint;
@@ -731,5 +746,3 @@
ioapic_assign_cluster(extint);
#endif
}
-
-#endif /* MIXED_MODE */
==== //depot/projects/hammer/sys/amd64/amd64/machdep.c#84 (text+ko) ====
==== //depot/projects/hammer/sys/amd64/amd64/mptable.c#24 (text+ko) ====
@@ -337,6 +337,7 @@
busses[i].bus_type = NOBUS;
/* Second, we run through adding I/O APIC's and busses. */
+ ioapic_enable_mixed_mode();
mptable_parse_apics_and_busses();
/* Third, we run through the table tweaking interrupt sources. */
==== //depot/projects/hammer/sys/amd64/include/apicvar.h#21 (text+ko) ====
@@ -137,6 +137,7 @@
void apic_register_enumerator(struct apic_enumerator *enumerator);
void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
int ioapic_disable_pin(void *cookie, u_int pin);
+void ioapic_enable_mixed_mode(void);
int ioapic_get_vector(void *cookie, u_int pin);
int ioapic_next_logical_cluster(void);
void ioapic_register(void *cookie);
==== //depot/projects/hammer/sys/amd64/isa/atpic.c#39 (text+ko) ====
@@ -63,6 +63,16 @@
#define SLAVE 1
/*
+ * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
+ * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
+ */
+#ifdef PC98
+#define ICU_SLAVEID 7
+#else
+#define ICU_SLAVEID 2
+#endif
+
+/*
* Determine the base master and slave modes not including auto EOI support.
* All machines that FreeBSD supports use 8086 mode.
*/
@@ -81,7 +91,8 @@
#define SLAVE_MODE BASE_SLAVE_MODE
#endif
-#define IMEN_MASK(ai) (1 << (ai)->at_irq)
+#define IRQ_MASK(irq) (1 << (irq))
+#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
#define NUM_ISA_IRQS 16
@@ -163,7 +174,7 @@
INTSRC(15),
};
-CTASSERT(sizeof(atintrs) / sizeof(struct atpic_intsrc) == NUM_ISA_IRQS);
+CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
static void
atpic_enable_source(struct intsrc *isrc)
@@ -201,7 +212,7 @@
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_1
mtx_lock_spin(&icu_lock);
- outb(atpics[MASTER].at_ioaddr, ICU_EOI);
+ outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
mtx_unlock_spin(&icu_lock);
#endif
}
@@ -218,9 +229,9 @@
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_2
mtx_lock_spin(&icu_lock);
- outb(atpics[SLAVE].at_ioaddr, ICU_EOI);
+ outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
#ifndef AUTO_EOI_1
- outb(atpics[MASTER].at_ioaddr, ICU_EOI);
+ outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
#endif
mtx_unlock_spin(&icu_lock);
#endif
@@ -337,9 +348,9 @@
* which line on the master we are connected to.
*/
if (slave)
- outb(imr_addr, ICU_SLAVEID); /* my slave id is 7 */
+ outb(imr_addr, ICU_SLAVEID);
else
- outb(imr_addr, IRQ_SLAVE); /* slave on line 7 */
+ outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
/* Set mode. */
if (slave)
@@ -389,8 +400,8 @@
* we have one and as an optimization to avoid masking edge
* triggered interrupts. For the case that we don't have an ELCR,
* it doesn't hurt to mask an edge triggered interrupt, so we
- * that is why we assume level trigger for any interrupt that we
- * aren't sure is edge triggered.
+ * assume level trigger for any interrupt that we aren't sure is
+ * edge triggered.
*/
if (elcr_probe() == 0) {
using_elcr = 1;
@@ -434,7 +445,7 @@
struct intsrc *isrc;
int vec = (uintptr_t)cookie;
- KASSERT(vec < ICU_LEN, ("unknown int %d\n", vec));
+ KASSERT(vec < NUM_ISA_IRQS, ("unknown int %d\n", vec));
isrc = &atintrs[vec].at_intsrc;
/*
@@ -454,7 +465,7 @@
isr = inb(port);
outb(port, OCW3_SEL | OCW3_RR);
mtx_unlock_spin(&icu_lock);
- if ((isr & IRQ7) == 0)
+ if ((isr & IRQ_MASK(7)) == 0)
return;
}
intr_execute_handlers(isrc, &iframe);
==== //depot/projects/hammer/sys/amd64/isa/atpic_vector.S#17 (text+ko) ====
@@ -37,8 +37,6 @@
*/
#include <machine/asmacros.h>
-#include <amd64/isa/icu.h>
-#include <amd64/isa/isa.h>
#include "assym.s"
==== //depot/projects/hammer/sys/amd64/isa/clock.c#22 (text+ko) ====
@@ -73,7 +73,6 @@
#endif
#include <machine/specialreg.h>
-#include <amd64/isa/icu.h>
#include <amd64/isa/isa.h>
#include <isa/rtc.h>
#ifdef DEV_ISA
==== //depot/projects/hammer/sys/amd64/isa/icu.h#20 (text+ko) ====
@@ -41,39 +41,9 @@
#ifndef _AMD64_ISA_ICU_H_
#define _AMD64_ISA_ICU_H_
-/*
- * Interrupt enable bits - in normal order of priority (which we change)
- */
-#define IRQ0 0x0001 /* highest priority - timer */
-#define IRQ1 0x0002
-#define IRQ_SLAVE 0x0004
-#define IRQ8 0x0100
-#define IRQ9 0x0200
-#define IRQ2 IRQ9
-#define IRQ10 0x0400
-#define IRQ11 0x0800
-#define IRQ12 0x1000
-#define IRQ13 0x2000
-#define IRQ14 0x4000
-#define IRQ15 0x8000
-#define IRQ3 0x0008 /* this is highest after rotation */
-#define IRQ4 0x0010
-#define IRQ5 0x0020
-#define IRQ6 0x0040
-#define IRQ7 0x0080 /* lowest - parallel printer */
-
-/*
- * Interrupt Control offset into Interrupt descriptor table (IDT)
- */
-#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
-#define ICU_LEN 16 /* 32-47 are ISA interrupts */
#define ICU_IMR_OFFSET 1
-#define ICU_SLAVEID 2
-#define ICU_EOI (OCW2_EOI) /* non-specific EOI */
-#ifndef LOCORE
void atpic_handle_intr(void *cookie, struct intrframe iframe);
void atpic_startup(void);
-#endif
#endif /* !_AMD64_ISA_ICU_H_ */
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