PERFORCE change 45020 for review

[John Baldwin]

http://perforce.freebsd.org/chv.cgi?CH=45020

Change 45020 by jhb at jhb_slimer on 2004/01/09 11:01:31

	Update todo lists.

Affected files ...

.. //depot/projects/smpng/sys/notes#3 edit
.. //depot/user/jhb/acpipci/notes#78 edit

Differences ...

==== //depot/projects/smpng/sys/notes#3 (text+ko) ====

@@ -36,14 +36,11 @@
 - Remove sched_lock from lockmgr TDF_DEADLKTREAT flag check.  Perhaps we
   can move this flag to TDP_DEADLKTREAT even.
   - Mostly untested
-- Allow mtx_trylock() to recurse on a recursive mutex.
-  - Needs strict testing
 - Use panic_thread pointer instead of panic_cpu to allow for migration
   of the panic'ing thread
   - Untested
-+ Move schedcpu() into its own kthread.
-  + Committed
-- Move loadav() into the schedcpu kthread.
+- Move loadav() into its own thread.
+  - Untested
 - Remove some bogus atomic_load_acq()'s and add ia32_pause()'s to
   stop_cpus() and restart_cpus().
   - Untested

==== //depot/user/jhb/acpipci/notes#78 (text+ko) ====

@@ -5,12 +5,14 @@
   + Allow loader tunables to override the IRQ for each link device.
   + Test routing of an unrouted link.
   - Trim includes in sys/i386/pci/pci_*.
+  - Only parse the PIR and create link devices if a PCIBIOS host-pci bridge
+    attaches.
 - Export PA's of APICs for vmware
 + Handle MADT and IRQ 9 special case
   - This is gross, we might want a redirection layer in nexus(4)
-  - Linux does this.  We just need to read the SCI int out of the FADT
+  + Linux does this.  We just need to read the SCI int out of the FADT
     instead of hard-coding 9.
-  - Use level/low if SCI routed to IRQ 9 as active/hi or if routed to
+  + Use level/low if SCI routed to IRQ 9 as active/hi or if routed to
     PCI interrupt
 + Add dev/ic/i8259A.h
 + Make acpi_cpu_c1() MD.
@@ -21,9 +23,11 @@
 - Allow SCI to be routed via mixed-mode?
 - Add a MI interrupt source abstraction and move handlers out of ithd and
   into that
+  - Have suspend/resume operate on pics, not individual sources
   - Defer creation of ithreads until a non-fast handler is added to an
     interrupt source
   - Kill isa_irq_pending()  (maybe, is this an MI function?)
+  - Lazily allocate PCI lapic interrupt vectors.
 - DDB
   - Add 'show ithread'
   + Add 'show irqs'
@@ -42,8 +46,8 @@
 + Implement mixed-mode and use it for IRQ0 unless no ExtINT pin or
   NO_MIXED_MODE
   + Add NO_MIXED_MODE option
+  - Make NO_MIXED_MODE a loader tunable as well.  (hw.apic.mixed_mode)
   - Add runtime decision for IRQ0 mixed mode?
-  - Don't use mixed mode with MADT?
 - Add handling of local APIC ERROR lvt.
 - Use the local apic timer to drive hard/stat/profclock (maybe too hard)
 - Do we need to be able to renumber I/O APICs?
@@ -52,7 +56,6 @@
   - Renumber I/O APIC IDs.  Ugh.  Not sure if this will have to be done for
     the general case or just for the mptable case.  Update: may not have to,
     it was a BIOS bug.  May have to bump NAPICID to 256 though.
-- Flesh out cpu topology map
 - Suspend/resume support for I/O APICs
 - reimplement lazy masking of interrupts for critical sections w/o bitmasks??
 - Support bus_config_intr()?
@@ -65,3 +68,6 @@
 Unrelated to this branch:
 - Work on cleaning up nested includes in sys/* headers.  According to Bruce,
   the only nested sys/* headers should be _*.h and queue.h.
+- Add commands to the loader to allow one to set hints via an intuitive
+  inteface, like 'disable apic0' sets 'hint.apic.0.disabled=1' or maybe
+  'devcfg disable apic0' 'devcfg set sio0 irq 4', 'devcfg delete foo0'