PERFORCE change 44804 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=44804

Change 44804 by jmallett at jmallett_oingo on 2004/01/04 21:19:53

	Or, y'know, I could have had no clue what I was doing and made
	a mistake due to not reading docs carefully.

Affected files ...

.. //depot/projects/mips/sys/mips/mips/tlb.c#19 edit

Differences ...

==== //depot/projects/mips/sys/mips/mips/tlb.c#19 (text+ko) ====

@@ -66,32 +66,12 @@
 static int tlb_maxasid = MIPS_TLB_NUM_ASIDS;
 #endif
 
-/*
- * Set up the page size, chop off the low PAGE_SHIFT bits,
- * and then shift off the upper bits.
- */
-static u_long
-tlb_pagemask(vm_size_t pageshift)
-{
-	u_long pm;
-
-	pm = ~0UL;
-	pm >>= PAGE_SHIFT + 1;
-	pm <<= PAGE_SHIFT + 1;
-	pm <<= 7;
-	pm >>= 7;
-
-	return (pm);
-}
-
 void
 tlb_bootstrap(vm_size_t pages, vm_offset_t (*ptalloc)(vm_size_t))
 {
 	pt_entry_t *pte;
 	vm_size_t i;
 
-	mips_wr_pagemask(tlb_pagemask(PAGE_SHIFT));
-
 	/*
 	 * Set up KPT.
 	 */
@@ -109,10 +89,11 @@
 	}
 
 	/*
-	 * Initialise ASID and clear TLB.
+	 * Initialise ASID and clear TLB and set up for 4K pages.
 	 */
 	mips_wr_entryhi(0);
 	tlb_invalidate_all();
+	mips_wr_pagemask(0); /* XXX 4K */
 
 	/*
 	 * Just one wired TLB entry.
@@ -186,7 +167,6 @@
 	mips_wr_entrylo0(pte0);
 	mips_wr_entrylo1(pte1);
 	mips_wr_entryhi(ehi);
-	mips_wr_pagemask(tlb_pagemask(PAGE_SHIFT));
 	if (i < 0)
 		mips_tlbwr();
 	else