PERFORCE change 67817 for review
Peter Wemm
peter at FreeBSD.org
Tue Dec 28 16:36:57 PST 2004
http://perforce.freebsd.org/chv.cgi?CH=67817
Change 67817 by peter at peter_daintree on 2004/12/29 00:36:49
merge i386 changes via i386_hammer branch
Affected files ...
.. //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#33 integrate
.. //depot/projects/hammer/sys/amd64/amd64/local_apic.c#40 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#79 integrate
.. //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#61 integrate
.. //depot/projects/hammer/sys/amd64/include/apicreg.h#10 integrate
.. //depot/projects/hammer/sys/amd64/include/apicvar.h#27 integrate
.. //depot/projects/hammer/sys/amd64/include/intr_machdep.h#15 integrate
.. //depot/projects/hammer/sys/amd64/isa/isa.c#13 integrate
.. //depot/projects/hammer/sys/amd64/pci/pci_cfgreg.c#17 integrate
Differences ...
==== //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#33 (text+ko) ====
@@ -286,6 +286,17 @@
is->is_straycount = &intrcnt[is->is_index + 1];
}
+void
+intrcnt_add(const char *name, u_long **countp)
+{
+
+ mtx_lock_spin(&intr_table_lock);
+ *countp = &intrcnt[intrcnt_index];
+ intrcnt_setname(name, intrcnt_index);
+ intrcnt_index++;
+ mtx_unlock_spin(&intr_table_lock);
+}
+
static void
intr_init(void *dummy __unused)
{
==== //depot/projects/hammer/sys/amd64/amd64/local_apic.c#40 (text+ko) ====
@@ -61,7 +61,9 @@
#define MAX_APICID 16
/* Sanity checks on IDT vectors. */
-CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS);
+CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
+CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
+CTASSERT(APIC_LOCAL_INTS == 240);
CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
/*
@@ -96,10 +98,10 @@
static struct lvt lvts[LVT_MAX + 1] = {
{ 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
{ 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
- { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Timer: needs a vector */
- { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Error: needs a vector */
+ { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
+ { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
{ 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* PMC */
- { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Thermal: needs a vector */
+ { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
};
static inthand_t *ioint_handlers[] = {
@@ -115,6 +117,9 @@
volatile lapic_t *lapic;
+static void lapic_enable(void);
+static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
+
static uint32_t
lvt_mode(struct lapic *la, u_int pin, uint32_t value)
{
@@ -148,11 +153,7 @@
/* Use a vector of 0. */
break;
case APIC_LVT_DM_FIXED:
-#if 0
value |= lvt->lvt_vector;
-#else
- panic("Fixed LINT pins not supported");
-#endif
break;
default:
panic("bad APIC LVT delivery mode: %#x\n", value);
@@ -166,7 +167,6 @@
void
lapic_init(uintptr_t addr)
{
- u_int32_t value;
/* Map the local APIC and setup the spurious interrupt handler. */
KASSERT(trunc_page(addr) == addr,
@@ -175,10 +175,7 @@
setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
/* Perform basic initialization of the BSP's local APIC. */
- value = lapic->svr;
- value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
- value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
- lapic->svr = value;
+ lapic_enable();
/* Set BSP's per-CPU local APIC ID. */
PCPU_SET(apic_id, lapic_id());
@@ -231,6 +228,9 @@
lapic->id, lapic->version, lapic->ldr, lapic->dfr);
printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
+ printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
+ lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
+ lapic->lvt_pcint);
}
void
@@ -257,17 +257,9 @@
eflags = intr_disable();
maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
- /* Program LINT[01] LVT entries. */
- lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
- lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
-
- /* XXX: more LVT entries */
+ /* Initialize the TPR to allow all interrupts. */
+ lapic_set_tpr(0);
- /* Clear the TPR. */
- value = lapic->tpr;
- value &= ~APIC_TPR_PRIO;
- lapic->tpr = value;
-
/* Use the cluster model for logical IDs. */
value = lapic->dfr;
value &= ~APIC_DFR_MODEL_MASK;
@@ -282,10 +274,14 @@
lapic->ldr = value;
/* Setup spurious vector and enable the local APIC. */
- value = lapic->svr;
- value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
- value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
- lapic->svr = value;
+ lapic_enable();
+
+ /* Program LINT[01] LVT entries. */
+ lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
+ lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
+
+ /* XXX: more LVT entries */
+
intr_restore(eflags);
}
@@ -300,6 +296,18 @@
lapic->svr = value;
}
+static void
+lapic_enable(void)
+{
+ u_int32_t value;
+
+ /* Program the spurious vector to enable the local APIC. */
+ value = lapic->svr;
+ value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
+ value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
+ lapic->svr = value;
+}
+
int
lapic_id(void)
{
@@ -471,6 +479,24 @@
return (0);
}
+/*
+ * Adjust the TPR of the current CPU so that it blocks all interrupts below
+ * the passed in vector.
+ */
+void
+lapic_set_tpr(u_int vector)
+{
+#ifdef CHEAP_TPR
+ lapic->tpr = vector;
+#else
+ u_int32_t tpr;
+
+ tpr = lapic->tpr & ~APIC_TPR_PRIO;
+ tpr |= vector;
+ lapic->tpr = tpr;
+#endif
+}
+
void
lapic_eoi(void)
{
@@ -637,10 +663,9 @@
#ifdef SMP
/*
* Inter Processor Interrupt functions. The lapic_ipi_*() functions are
- * private the sys/i386 code. The public interface for the rest of the
+ * private to the sys/i386 code. The public interface for the rest of the
* kernel is defined in mp_machdep.c.
*/
-
int
lapic_ipi_wait(int delay)
{
@@ -745,7 +770,7 @@
* the failure with the check above when the next IPI is
* sent.
*
- * We could skiip this wait entirely, EXCEPT it probably
+ * We could skip this wait entirely, EXCEPT it probably
* protects us from other routines that assume that the
* message was delivered and acted upon when this function
* returns.
==== //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#79 (text+ko) ====
@@ -915,8 +915,8 @@
ipi_selected(map, IPI_HARDCLOCK);
}
-
-void ipi_bitmap_handler(struct clockframe frame)
+void
+ipi_bitmap_handler(struct clockframe frame)
{
int cpu = PCPU_GET(cpuid);
u_int ipi_bitmap;
@@ -950,7 +950,6 @@
critical_exit();
}
-
/*
* send an IPI to a set of cpus.
*/
==== //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#61 (text+ko) ====
==== //depot/projects/hammer/sys/amd64/include/apicreg.h#10 (text+ko) ====
@@ -330,7 +330,12 @@
#define APIC_LVTT_DS 0x00001000
#define APIC_LVTT_M 0x00010000
#define APIC_LVTT_TM 0x00020000
+# define APIC_LVTT_TM_ONE_SHOT 0x00000000
+# define APIC_LVTT_TM_PERIODIC 0x00020000
+
+/* APIC timer current count */
+#define APIC_TIMER_MAX_COUNT 0xffffffff
/* fields in TDCR */
#define APIC_TDCR_2 0x00
==== //depot/projects/hammer/sys/amd64/include/apicvar.h#27 (text+ko) ====
@@ -44,7 +44,7 @@
* 0xff (255) +-------------+
* | | 15 (Spurious / IPIs / Local Interrupts)
* 0xf0 (240) +-------------+
- * | | 14 (I/O Interrupts)
+ * | | 14 (I/O Interrupts / Timer)
* 0xe0 (224) +-------------+
* | | 13 (I/O Interrupts)
* 0xd0 (208) +-------------+
@@ -80,8 +80,13 @@
*/
#define APIC_ID_ALL 0xff
+
+/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
#define APIC_IO_INTS (IDT_IO_INTS + 16)
-#define APIC_NUM_IOINTS 192
+#define APIC_NUM_IOINTS 191
+
+/* The timer interrupt is used for clock handling and drives hardclock, etc. */
+#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
/*
********************* !!! WARNING !!! ******************************
@@ -103,15 +108,12 @@
* other deadlocks caused by IPI_STOP.
*/
+/* Interrupts for local APIC LVT entries other than the timer. */
#define APIC_LOCAL_INTS 240
+#define APIC_ERROR_INT APIC_LOCAL_INTS
+#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
-#if 0
-#define APIC_TIMER_INT (APIC_LOCAL_INTS + X)
-#define APIC_ERROR_INT (APIC_LOCAL_INTS + X)
-#define APIC_THERMAL_INT (APIC_LOCAL_INTS + X)
-#endif
-
-#define APIC_IPI_INTS (APIC_LOCAL_INTS + 0)
+#define APIC_IPI_INTS (APIC_LOCAL_INTS + 2)
#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
#define IPI_INVLPG (APIC_IPI_INTS + 2)
@@ -128,7 +130,8 @@
#define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
-/* The spurious interrupt can share the priority class with the IPIs since
+/*
+ * The spurious interrupt can share the priority class with the IPIs since
* it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
*/
#define APIC_SPURIOUS_INT 255
@@ -207,6 +210,7 @@
enum intr_polarity pol);
int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
enum intr_trigger trigger);
+void lapic_set_tpr(u_int vector);
void lapic_setup(void);
#endif /* !LOCORE */
==== //depot/projects/hammer/sys/amd64/include/intr_machdep.h#15 (text+ko) ====
@@ -100,6 +100,7 @@
int intr_remove_handler(void *cookie);
void intr_resume(void);
void intr_suspend(void);
+void intrcnt_add(const char *name, u_long **countp);
#endif /* !LOCORE */
#endif /* _KERNEL */
==== //depot/projects/hammer/sys/amd64/isa/isa.c#13 (text+ko) ====
==== //depot/projects/hammer/sys/amd64/pci/pci_cfgreg.c#17 (text+ko) ====
@@ -325,4 +325,3 @@
devmax = 0;
return (cfgmech);
}
-
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